SLVS520C March   2006  – October 2015 TPS63000 , TPS63001 , TPS63002

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Enable
      2. 7.3.2 Undervoltage Lockout
      3. 7.3.3 Overtemperature Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Soft-Start and Short Circuit Protection
      2. 7.4.2 Buck-Boost Operation
      3. 7.4.3 Power-Save Mode and Synchronization
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Programming the Output Voltage
        2. 8.2.2.2 Inductor Selection
        3. 8.2.2.3 Capacitor Selection
          1. 8.2.2.3.1 Input Capacitor
          2. 8.2.2.3.2 Output Capacitor
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Related Links
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

DRC Package
10-Pin VSON
Top View
TPS63000 TPS63001 TPS63002 po_slvs520.gif
1. The exposed thermal pad is connected to PGND.

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
EN 6 IN Enable input (1 enabled, 0 disabled)
FB 10 IN Voltage feedback of adjustable versions, must be connected to VOUT on fixed output voltage versions
GND 9 — Control / logic ground
L1 4 IN Connection for inductor
L2 2 IN Connection for inductor
PGND 3 — Power ground
PS/SYNC 7 IN Enable / disable power-save mode (1 disabled, 0 enabled, clock signal for synchronization)
VIN 5 IN Supply voltage for power stage
VINA 8 IN Supply voltage for control stage
VOUT 1 OUT Buck-boost converter output
Exposed Thermal Pad — — The exposed thermal pad is connected to PGND.