SLVSH51 july   2023 TPS631012 , TPS631013

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Rating
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics 
    6. 7.6 Timing Requirements
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Undervoltage Lockout (UVLO)
      2. 8.3.2 Enable and Soft Start
      3. 8.3.3 Device Enable (EN)
      4. 8.3.4 Output Voltage Control
      5. 8.3.5 Mode Selection (PFM/FPWM)
      6. 8.3.6 Output Discharge
      7. 8.3.7 Reverse Current Operation
      8. 8.3.8 Protection Features
        1. 8.3.8.1 Input Overvoltage Protection
        2. 8.3.8.2 Output Overvoltage Protection
        3. 8.3.8.3 Short Circuit Protection/Hiccup
        4. 8.3.8.4 Thermal Shutdown
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
      1. 8.5.1 Serial Interface Description
      2. 8.5.2 Standard-, Fast-, and Fast-Mode Plus Protocol
      3. 8.5.3 I2C Update Sequence
    6. 8.6 Register Map
      1. 8.6.1 Register Description
        1. 8.6.1.1 Register Map
        2. 8.6.1.2 Register CONTROL1 (Register address: 0x02; Default: 0x08)
        3. 8.6.1.3 Register VOUT (Register address: 0x03; Default: 0x5C)
        4. 8.6.1.4 Register CONTROL2 (Register address: 0x05; Default: 0x45)
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Output Capacitor Selection
        3. 9.2.2.3 Input Capacitor Selection
        4. 9.2.2.4 Setting the Output Voltage
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.6.1.4 Register CONTROL2 (Register address: 0x05; Default: 0x45)

Return to Register Map

Table 8-7 Register CONTROL2 Format
7 6 5 4 3 2 1 0
FPWM FAST_RAMP_EN EN_DISCH_VOUT[1:0] CL_RAMP_MIN TD_RAMP[2:0]
R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write

Table 8-8 Register CONTROL2 Field Descriptions
BitFieldTypeResetDescription
7FPWMR/W0b0Force PWM operation

0 : DISABLE, 1 : ENABLE

6FAST_RAMP_ENR/W0b1Device can start-up faster than VOUT ramp

0 : DISABLE, 1 : ENABLE

5:4EN_DISCH_VOUT[1:0]R/W0b00Enable of BUBO Vout Discharge

00 : DISABLE

01 : SLOW (34mA)

10 : MEDIUM (67mA)

11 : FAST (100mA)

3CL_RAMP_MINR/W0b0Define the minimum current limit during the soft start ramp

0 : Low (500mA)

1 : High (2x Low)

2:0TD_RAMP[2:0]R/W0b101Defines the ramp time for the Vo soft start ramp

000: 0.256ms

001: 0.512ms

010: 1.024ms

011: 1.920ms

100: 3.584ms

101: 7.552ms

110: 9.600ms

111: 24.320ms