SLVSD44A September   2017  – July 2018 TPS63710

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application
      2.      Efficiency vs output current for VOUT = -1.8V
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1. Table 1. Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Low Noise Reference System
      2. 7.3.2 Duty Cycle
      3. 7.3.3 Enable
      4. 7.3.4 Undervoltage Lockout
      5. 7.3.5 Thermal Shutdown
      6. 7.3.6 Power Good Output
    4. 7.4 Device Functional Modes
      1. 7.4.1 Soft-Start
      2. 7.4.2 VOUT Discharge
      3. 7.4.3 Current Limit
      4. 7.4.4 CCP Capacitor Precharge
      5. 7.4.5 PWM Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Setting the Output Voltage
        3. 8.2.2.3 Inductor Selection
        4. 8.2.2.4 Capacitor Selection
          1. 8.2.2.4.1 CCP Capacitor
          2. 8.2.2.4.2 Input Capacitor
          3. 8.2.2.4.3 Output Capacitor
      3. 8.2.3 Application Curves
        1. 8.2.3.1 Parameter Measurement Information
    3. 8.3 System Examples
      1. 8.3.1 Typical Application for Powering the Negative Rail of a Gallium Nitride (GaN) Power Amplifier
      2. 8.3.2 Typical Application for Powering the Negative Rail of an ADC or DAC
      3. 8.3.3 Typical Application for Laser Diode Bias
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Custom Design With WEBENCH® Tools
      2. 11.1.2 Third-Party Products Disclaimer
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

TJ = –40°C to 125°C, over recommended input voltage range. Typical values are at VIN = 5 V and TJ = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
I(Q) Quiescent supply current IOUT = 0mA, EN = high 15 mA
ISD Shutdown supply current EN = low, TJ = -40°C to 85°C (1) 5 25 μA
ISD Shutdown supply current EN = low, TJ = -40°C to 125°C (1) 55 μA
VUVLO Undervoltage lockout threshold VIN falling, detected at VAUX 2.55 2.6 2.7 V
Undervoltage lockout hysteresis VIN rising, detected at VAUX 250 350 mV
TSD Thermal shutdown temperature Junction temperature rising 160 °C
Thermal shutdown hysteresis Junction temperature falling 20 °C
CONTROL (EN, PG)
VIH High level input voltage for EN 1 14 V
VIL Low level input voltage for EN 0.4 V
IIN Input current for EN EN = high 0.01 0.1 μA
RIN Input resistance for EN EN = low 400 kΩ
PG de-glitch time rising or falling 10 µs
VOL_PG PG output low voltage IPG = 1 mA 0.07 0.3 V
ILKG_PG Input leakage current (PG) VPG = 5 V 100 nA
VVAUX Voltage at VAUX VIN ≥ 5 V, IVAUX = 100 µA 4.6 V
IVAUX Current drawn from VAUX 0 100 μA
POWER SWITCH
ILIM Switch current limit (LSD) 4 V ≤ VIN < 14 V, duty cycle ≤ 70% 1.4 2.1 3 A
ILIM Switch current limit (LSD) 3.1 V < VIN < 4 V, duty cycle ≤ 70% 0.8 A
RDS(ON) Switch on-resistance HSD switch, VIN ≥ 5 V 80 130 mΩ
LSD switch, VIN ≥ 5 V 120 190
RECT switch, VIN ≥ 5 V 40 80
DMAX Maximum duty cycle at SW pin 70%
ton,min Minimum on-time 130 ns
fS Switching frequency 1400 1500 1600 kHz
OUTPUT
VOUT Output voltage range |VOUT| < 0.7 x VIN -5.5 -1 V
VFB FB regulation voltage -0.7(2) V
Output voltage tolerance (3) for VOUT ≤ –1.8 V -1.5% 1.5%
Output voltage tolerance (3) for –1.8 V < VOUT ≤ –1 V -2% 1.5%
IFB Feedback input bias current VFB = –0.7 V 2 100 nA
RDIS Discharge resistance from pin VOUT to GND EN = low 100 Ω
Line regulation 0.05 %/A
Load regulation 0.02 %/V
tdelay Start-up delay time from EN = high to start switching with CCP = 10 µF 5 ms
tramp Ramp time from start switching until device has reached 95% of its nominal output voltage CCAP = 47 nF, VOUT = -1.8 V, device not in current limit during start-up 1 ms
Iramp Soft-start current into CCAP 55 100 145 µA
(1) This specification applies after there has been a high to low transition on EN. If EN is low while the supply voltage is applied, the shutdown current can be up to 90µA.
(2) Please see the application section for how to set the output voltage.
(3) Tolerance of VFB voltage and error of gain stage - see also "Low Noise Reference System"