SLVSD44A September 2017 – July 2018 TPS63710
PRODUCTION DATA.
The output voltage of the TPS63710 converter is adjusted with an external resistor divider connected to the FB pin. The voltage at the feedback pin is negative and is regulated to -0.7 V. The gain stage adds a gain factor of 1/0.9 such that the output voltage is -0.778 V for -0.7 V of FB voltage. See Low Noise Reference System for details.
The value of the output voltage is set by the selection of the resistive divider using Equation 3 and VFB_SET = -0.778 V. Both VOUT and VFB_SET are negative, so the ratio is positive again.
It is recommended to choose resistor values such that R1 + R2 are in a range from 100 kΩ to 500 kΩ. For example, if an output voltage of -1.8 V is needed and a resistor of 150-kΩ has been chosen for R2, a 196-kΩ resistor on R1 is required to program the desired output voltage.
Output Voltage | R1 | R2 |
---|---|---|
-1 V | 51.1 kΩ | 180 kΩ |
-1.8 V | 196 kΩ | 150 kΩ |
-2.5 V | 287 kΩ | 130 kΩ |
-5 V | 130 kΩ | 24 kΩ |
For proper regulation, the minimum input voltage should remain at least above the output voltage, per Equation 4:
See Figure 36 to Figure 38 for the recommended input voltage levels to generate a specific output voltage.