SLVSC45C August   2013  – June 2017 TPS65000-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Step-Down Converter
      2. 7.3.2 Soft Start
      3. 7.3.3 Linear Regulators
      4. 7.3.4 Oscillator and Spread-Spectrum Clock Generation
      5. 7.3.5 Power Good
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Filter Design (Inductor and Output Capacitor)
          1. 8.2.2.1.1 Inductor Selection
          2. 8.2.2.1.2 Output Capacitor Selection
          3. 8.2.2.1.3 Input Capacitor Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Input voltage On all pins except AGND, PGND, EN_DCDC, VLDO1, VLDO2, FB_LDO1, FB_LDO2, FB_DCDC pins with respect to AGND –0.3 7 V
On EN_DCDC with respect to AGND –0.3 VIN + 0.3, ≤ 7
Output voltage On VLDO1, VLDO2, FB_LDO1, FB_LDO2, FB_DCDC –0.3 3.6 V
Current VINDCDC, SW, PGND, 1800 mA
VINLDO1, VINLDO2, VLDO1, VLDO1, AGND 800 mA
At all other pins 1 mA
Operating free-air temperature, TA –40 105 °C
Maximum junction temperature, TJ 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1) ±2500 V
Charged device model (CDM), per AEC Q100-011 Corner pins (1, 4, 5, 8, 9, 12, 13, and 16) ±750
Other pins ±500
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

MIN NOM MAX UNIT
L1 SW pin inductor 1.5 2.2 3.3 μH
CI Input capacitor at VINDCDC 10 μF
Input capacitor at VINLDO1, VINLDO2 2.2 μF
CO Output capacitor for VDCDC 10 22 μF
Output capacitor for LDO1, LDO2 2.2 μF
IO DC-DC converter output current 600 mA
LDO1 output current 300 mA
LDO2 output current 300 mA
TA Operating ambient temperature –40 105 °C

6.4 Thermal Information

THERMAL METRIC(1) TPS65000-Q1 UNIT
RTE (WQFN)
16 PINS
RθJA Junction-to-ambient thermal resistance 46.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 56.1 °C/W
RθJB Junction-to-board thermal resistance 19.2 °C/W
ψJT Junction-to-top characterization parameter 1.1 °C/W
ψJB Junction-to-board characterization parameter 19.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 5.4 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

Over full operating ambient temperature range, typical values are at TA = 25° C. Unless otherwise noted, specifications apply for condition VIN = EN_LDOx = EN_DCDC = 3.6 V. External components L = 2.2 μH, COUT = 10 μF, CIN = 4.7 μF.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OPERATING VOLTAGE
VIN Input voltage for VINDCDC of DC-DC converter 2.3 6 V
Input voltage for LDO1 (VINLDO1) See (1) 1.6 6 V
Input voltage for LDO2 (VINLDO2) See (1) 1.6 6 V
Internal undervoltage (UVLO) lockout threshold VCC falling 1.72 1.77 1.82 V
Internal undervoltage (UVLO) lockout hysteresis 160 mV
SUPPLY CURRENT
IQ Operating quiescent current MODE low, EN_DCDC high,
EN_LDO1, EN_LDO2 low,
IOUT = 0 mA and no switching		 23 32 μA
MODE low, EN_DCDC low,
EN_LDO1, EN_LDO2 high, IOUT = 0 mA
IOUT = 0 mA and no switching		 50 57
EN_DCDC high, MODE high,
EN_LDO1, EN_LDO2 low, IOUT = 0 mA 		4 mA
ISD Shutdown Current EN_DCDC low EN_LDO1 and EN_LDO2 low 0.16 2.2 μA
DIGITAL PINS (EN_DCDC, EN_LDO1, EN_LDO2, MODE, PG
VIH High-level input voltage 1.2 V
VIL Low-level input voltage 0.4 V
VOL Low-level output voltage PG pins only, IO = –100 μA 0.4 V
Ilkg Input leakage current MODE, EN_DCDC, EN_LDO1, EN_LDO2 tied to GND or VINDCDC 0.01 0.1 μA
OSCILLATOR
fSW Oscillator frequency SSCG enabled, SSC modulation ratio = 16% 1.722 2.25 2.847 MHz
SSCG disabled, SSC modulation ratio disabled 2.01 2.25 2.41
STEP-DOWN CONVERTER POWER SWITCH
rDS(on) High-side MOSFET ON-resistance VINDCDC = VGS = 3.6 V 240 480 mΩ
Low-side MOSFET ON-resistance VINDCDC = VGS = 3.6 V 185 380 mΩ
IO DC output current 2.3 V ≤ VINDCDC ≤ 2.5 V 300 mA
2.5 V ≤ VINDCDC ≤ 6 V 600
ILIMF Forward current limit, PMOS and NMOS 2.3 V ≤ VINDCDC ≤ 6 V 800 1000 1400 mA
STEP-DOWN CONVERTER POWER SWITCH (continued)
TSD Thermal shutdown Increasing junction temperature 150 °C
Thermal shutdown hysteresis Decreasing junction temperature 30 °C
STEP-DOWN CONVERTER OUTPUT VOLTAGE
VDCDC Adjustable output voltage range, VDCDC 0.6 VINDCDC V
FB_DCDC pin current 0.1 μA
Vref Internal reference voltage 0.594 0.6 0.606 V
VDCDC Output-voltage accuracy (PWM mode)(2) MODE = high,
2.3 ≤ VINDCDC  ≤ 6 V		 –1.5% 0% 1.5%
Output-voltage accuracy (PFM mode) (3) MODE low
+1% voltage positioning active 		1%
Load regulation (PWM mode) MODE high 0.5 %/A
RDIS Internal discharge resistance at SW EN_DCDC low 450 Ω
LOW-DROPOUT REGULATORS
VI Input voltage for LDOx (VINLDOx) 1.6 6 V
VO Adjustable output voltage, LDOx (VLDOx)(4) 0.73 VINLDOx – VDO V
IO Continuous-pass FET current 300 mA
ISC Short-circuit current limit 2.3 V ≤ VINLDOx 340 700 mA
VINLDOx < 2.3 V 210 700
FB_LDOx pin current 0.1 μA
FB_LDOx voltage Adjustable VOUT mode only 0.5 V
VDO Dropout voltage (5) VINLDOx ≥ 2.3 V, IOUT = 250 mA 370 mV
VINLDOx < 2.3 V, IOUT = 175 mA 370 mV
Output voltage accuracy (6) IO = 1 mA to 300 mA, VINLDOx = 2.3 V–6 V,
VLDOx = 1.2 V		 –3.5% 3.5%
IO = 1 mA to 175 mA, VINLDOx = 1.6 V–6 V,
VLDOx = 1.2 V		 –3.5% 3.5%
Load regulation IO = 1 mA to 300 mA, VINLDOx = 3.6 V
VLDOx = 1.2 V		 –1.5% 1.5%
Line regulation VINLDOx = 1.6 V–6 V, VLDOx = 1.2 V at
IO = 1 mA		 –0.5% 0.5%
PSRR Power-supply rejection ratio fNOISE ≤ 10 kHz, COUT ≥ 2.2 μF, VIN = 2.3 V,
VOUT = 1.3 V, IOUT = 10 mA		 40 dB
RDIS Internal discharge resistance at VLDOx EN_LDOx low 450 Ω
TSD Thermal shutdown Increasing temperature 150 °C
Thermal shutdown hysteresis Decreasing temperature 30 °C
(1) The design principle allows only VINDCDC to be the highest supply in the system. If separate input voltage supplies are used for the DC-DC converter and LDOs, then choose VINDCDC ≥ VINLDO1 and VINDCDC ≥ VINLDO2.
(2) For VINDCDC = VDCDC + 1 V
(3) In PFM mode, the internal reference voltage is typically 1.01 × VREF.
(4) Maximum output voltage VLDOx = 3.6 V.
(5) VDO = VINLDOx – VLDOx, where VINLDOx = VLDOx(nom) – 100 mV
(6) Output voltage specification does not include tolerance of external programming resistors.

6.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STEP-DOWN CONVERTER OUTPUT VOLTAGE
tStart Start-up time EN_DCDC to start of switching (10%) 250 µs
tRamp VDCDC ramp-up time VDCDC ramp from 10% to 90% 250 µs
LOW-DROPOUT REGULATORS
tRAMP VLDOx ramp time VLDOx ramp from 10% to 90% 200 µs

6.7 Typical Characteristics

TPS65000-Q1 vo_v_io_pfm_lvs810.gif Figure 1. Efficiency (DC-DC 600-mA PFM Mode)
vs Output Current
TPS65000-Q1 voripp_pfm_lvs810.gif Figure 3. Output Voltage Ripple (DC-DC PFM Mode)
TPS65000-Q1 dc_start_time_lvs810.gif Figure 5. Start-Up Timing (DC-DC)
TPS65000-Q1 lt_dc_pfm_lvs810.gif Figure 7. Line Transient Response (DC-DC PFM Mode)
TPS65000-Q1 lt_ldo2_lvs810.gif Figure 9. Line Transient Response (LDOx)
TPS65000-Q1 lt2_dc_pwm_lvs810.gif Figure 11. Load Transient Response (DC-DC PWM Mode)
TPS65000-Q1 pfm_to_pwm_lvs810.gif Figure 13. PFM to PWM Transition (DC-DC)
TPS65000-Q1 pddr_ldo1_lvs810.gif Figure 15. Power-Supply Rejection Ratio (LDOx) vs Frequency
TPS65000-Q1 vo_v_io_pwm_lvs810.gif Figure 2. Efficiency (DC-DC 600-mA PWM Mode)
vs Output Current
TPS65000-Q1 voripp_pwm_lvs810.gif Figure 4. Output Voltage Ripple (DC-DC PWM Mode)
TPS65000-Q1 ldo1_start_time_lvs810.gif Figure 6. Start-Up Timing (LDOx)
TPS65000-Q1 lt_dc_pwm_lvs810.gif Figure 8. Line Transient Response (DC-DC PWM Mode)
TPS65000-Q1 lt2_dc_pfm_lvs810.gif Figure 10. Load Transient Response (DC-DC PFM Mode)
TPS65000-Q1 lt_ldo1_lvs810.gif Figure 12. Load Transient Response (LDOx)
TPS65000-Q1 pwm_to_pfm_lvs810.gif Figure 14. PWM to PFM Transition (DC-DC)