The TPS65011 device is an integrated power and battery management IC for applications powered by one Li-Ion or Li-Polymer cell and which require multiple power rails. The TPS65011 provides two highly efficient, 1.25-MHz step-down converters targeted at providing the core voltage and peripheral, I/O rails in a processor-based system. Both step-down converters enter a low-power mode at light load for maximum efficiency across the widest possible range of load currents.
The TPS65011 also integrates two 200-mA LDO voltage regulators, which are enabled via the serial interface. Each LDO operates with an input voltage range between 1.8 V and 6.5 V, allowing them to be supplied from one of the step-down converters or directly from the battery.
The TPS65011 also has a highly integrated and flexible Li-Ion linear charger and system power management. It offers integrated USB-port and AC-adapter supply management with autonomous power-source selection, power FET and current sensor, high accuracy current and voltage regulation, charge status, and charge termination.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS65011 | VQFN (48) | 7.00 mm × 7.00 mm |
Changes from A Revision (January 2005) to B Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
CHARGER SECTION | |||
AC | 40 | I | Charger input voltage from AC adapter. The AC pin can be left open or can be connected to ground if the charger is not used. |
AGND2 | 44 | — | Analog ground connection. All analog ground pins are connected internally on the chip. |
ISET | 37 | I | External charge current setting resistor connection for use with AC adapter |
PG | 11 | O | Indicates when a valid power supply is present for the charger (open drain) |
Thermal Pad | - | — | Connect the thermal pad to GND |
TS | 38 | I | Battery temperature sense input |
USB | 43 | I | Charger input voltage from USB port. The USB pin can be left open or can be connected to ground if the charger is not used. |
VBAT_A | 41 | I | Sense input for the battery voltage. Connect directly with the battery. |
VBAT_B | 42 | O | Power output of the battery charger. Connect directly with the battery. |
SWITCHING REGULATOR SECTION | |||
AGND3 | 45 | — | Analog ground connection. All analog ground pins are connected internally on the chip. |
L1_A | 9 | — | Switch pin of VMAIN converter. The VMAIN inductor is connected here. |
L1_B | 10 | ||
L2 | 4 | — | Switch pin of VCORE converter. The VCORE inductor is connected here. |
PGND1_A | 15 | — | Power ground for VMAIN converter |
PGND1_B | 16 | ||
PGND2 | 46 | — | Power ground for VCORE converter |
VCC | 6 | I | Power supply for digital and analog circuitry of MAIN and CORE DC-DC converters. This must be connected to the same voltage supply as VINCORE and VINMAIN. Also supplies serial interface block |
VCORE | 48 | I | VCORE feedback voltage sense input, connect directly to VCORE |
VINCORE | 5 | I | Input voltage for VCORE step-down converter. This must be connected to the same voltage supply as VINMAIN and VCC. |
VINMAIN_A | 7 | I | Input voltage for VMAIN step-down converter. This must be connected to the same voltage supply as VINCORE and VCC. |
VINMAIN_B | 8 | ||
VMAIN | 13 | I | VMAIN feedback voltage sense input, connect directly to VMAIN |
LDO REGULATOR SECTION | |||
AGND1 | 21 | — | Analog ground connection. All analog ground pins are connected internally on the chip. |
VFB_LDO1 | 23 | I | Feedback input from external resistive divider for LDO1 |
VINLDO1 | 22 | I | Input voltage for LDO1 |
VINLDO2 | 19 | I | Input voltage for LDO2 |
VLDO1 | 24 | O | Output voltage for LDO1 |
VLDO2 | 20 | O | Output and feedback voltage for LDO2 |
DRIVER SECTION | |||
LED2 | 2 | O | LED driver, with blink rate programmable via serial interface |
VIB | 3 | O | Vibrator driver, enabled via serial interface |
CONTROL AND I2C SECTION | |||
BATT_COVER | 39 | I | Indicates if battery cover is in place |
DEFCORE | 1 | I | Input signal indicating default VCORE voltage, 0 = 1.3 V, 1 = 1.6 V |
DEFMAIN | 12 | I | Input signal indicating default VMAIN voltage, 0 = 1.8 V, 1 = 3.3 V |
GPIO1 | 26 | I/O | General-purpose open-drain input/output |
GPIO2 | 25 | I/O | General-purpose open-drain input/output |
GPIO3 | 18 | I/O | General-purpose open-drain input/output |
GPIO4 | 17 | I/O | General-purpose open-drain input/output |
HOT_RESET | 31 | I | Push-button reset input used to reboot or wakeup processor via TPS65013 |
IFLSB | 28 | I | LSB of serial interface address used to distinguish two devices with the same address |
INT | 35 | O | Indicates a charge fault or termination, or if any of the regulator outputs are below the lower tolerance level, active low (open drain) |
LOW_PWR | 36 | I | Input signal indicating deep-sleep mode, VCORE is lowered to predefined value or disabled |
MPU_RESET | 32 | O | Open-drain reset output generated by user activated HOT_RESET |
PB_ONOFF | 47 | I | Push-button enable pin, also used to wakeup processor from low-power mode |
PS_SEQ | 14 | I | Sets power-up/down sequence of step-down converters |
PWRFAIL | 34 | O | Open-drain output. Active low when UVLO comparator indicates low VBAT condition or when shutdown is about to occur due to an overtemperature condition or when the battery cover is removed (BATT_COVER has gone low). |
RESPWRON | 33 | O | Open-drain system reset output, generated according to the state of the VMAIN output voltage. If the main output is disabled, RESPWRON is active (i.e., low). |
SCLK | 30 | I | Serial interface clock line |
SDAT | 29 | I/O | Serial interface data/address |
TPOR | 27 | I | Sets the reset delay time at RESPWRON. TPOR = 0: Tn(RESPWRON) = 100 ms. TPOR = 1: Tn(RESPWRON) = 1 s. |
MIN | MAX | UNIT | |
---|---|---|---|
Input voltage on VAC pin with respect to AGND | 20 | V | |
Input voltage range on all other pins except AGND/PGND pins with respect to AGND | -0.3 | 7 | V |
HBM and CDM capabilities at pins VIB, PG, and LED2 | 1 | kV | |
Current at AC, VBAT, VINMAIN, L1, PGND1 | 1800 | mA | |
Peak current at all other pins | 1000 | mA | |
Continuous power dissipation | See Dissipation Ratings | ||
Operating free-air temperature, TA | -40 | 85 | °C |
Maximum junction temperature, TJ | 125 | °C | |
Storage temperature range, Tstg | -65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) | 1000 | V |
Charged device model (CDM), per JEDEC specification JESD22-C101(2) | 1000 | V |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
V(AC) | Supply voltage from AC adapter | 4.5 | 5.5 | V | |
V(USB) | Supply voltage from USB | 4.4 | 5.25 | V | |
V(BAT) | Voltage at battery charger | 2.5 | 4.2 | V | |
VI(MAIN),VI(CORE),VCC | Input voltage range step-down converters | 2.5 | 6.0 | V | |
VI(LDO1), VI(LDO2) | Input voltage range for LDOs | 1.8 | 6.5 | V | |
TA | Operating ambient temperature | -40 | 85 | °C | |
TJ | Operating junction temperature | -40 | 125 | °C | |
R(CC) | Resistor from VI(main),VI(core) to VCC used for filtering, CI(VCC) = 1 µF | 10 | 100 | Ω |
THERMAL METRIC(1) | TPS65011 | UNIT | |
---|---|---|---|
RGZ (VQFN) | |||
48 PIN | |||
RθJA | Junction-to-ambient thermal resistance | 27.0 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 14.3 | °C/W |
RθJB | Junction-to-board thermal resistance | 4.6 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.2 | °C/W |
ψJB | Junction-to-board characterization parameter | 4.6 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 1.1 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
CONTROL SIGNALS: LOW_PWR, SCLK, SDAT (INPUT) | |||||||
VIH | High level input voltage | IIH = 20 µA (1) | 2 | VCC | V | ||
VIL | Low level input voltage | IIL = 10 µA | 0 | 0.8 | V | ||
IIB | Input bias current | 0.01 | 1.0 | µA | |||
CONTROL SIGNALS: PB_ONOFF, HOT_RESET, BATT_COVER | |||||||
VIH | High level input voltage | IIH = 20 µA(1) | 0.8 VCC | 6 | V | ||
VIL | Low level input voltage | IIL = 10 µA | 0 | 0.4 | V | ||
R(pb_onoff) | Pulldown resistor at PB_ONOFF | 1000 | kΩ | ||||
R(hot_reset) | Pullup resistor at HOT_RESET, connected to VCC |
1000 | kΩ | ||||
R(batt_cover) | Pulldown resistor at BATT_COVER | 2000 | kΩ | ||||
t(glitch) | De-glitch time at all 3 pins | 38 | 56 | 77 | ms | ||
t(batt_cover) | Delay after t(glitch) (PWRFAIL goes low) before supplies are disabled when BATT_COVER goes low. | 1.68 | 2.4 | 3.2 | ms | ||
CONTROL SIGNALS: MPU_RESET, PWRFAIL, RESPWRON, INT, SDAT (OUTPUT) | |||||||
VOH | High level output voltage | 6 | V | ||||
VOL | Low level output voltage | IIL = 10 mA | 0 | 0.3 | V | ||
td(mpu_nreset) | Duration of low pulse at MPU_RESET | 100 | µs | ||||
td(nrespwron) | Duration of low pulse at RESPWRON after VMAIN is in regulation | TPOR = 0 | 80 | 100 | 120 | ms | |
TPOR = 1 | 800 | 1000 | 1200 | ||||
td(uvlo) | Time between UVLO going active (PWRFAIL going low) and supplies being disabled | 1.68 | 2.4 | 3.2 | ms | ||
td(overtemp) | Time between chip overtemperature condition being recognized (PWRFAIL going low) and supplies being disabled | 1.68 | 2.4 | 3.2 | ms | ||
SUPPLY PIN: VCC | |||||||
I(Q) | Operating quiescent current | VI = 3.6 V, current into Main + Core + VCC | 70 | µA | |||
IO(SD) | Shutdown supply current | VI = 3.6 V, BATT_COVER = GND, Current into Main + Core + VCC |
15 | 25 | µA | ||
VMAIN STEP-DOWN CONVERTER | |||||||
VI | Input voltage range | 2.5 | 6.0 | V | |||
IO | Maximum output current | 1000 | mA | ||||
IO(SD) | Shutdown supply current | BATT_COVER = GND | 0.1 | 1 | µA | ||
rDS(on) | P-channel MOSFET on-resistance | VI(MAIN) = VGS = 3.6 V | 110 | 210 | mΩ | ||
Ilkg(p) | P-channel leakage current | V(DS) = 6.0 V | 1 | µA | |||
rDS(on) | N-channel MOSFET on-resistance | VI(MAIN) = VGS = 3.6 V | 110 | 200 | mΩ | ||
Ilkg(N) | N-channel leakage current | V(DS) = 6.0 V | 1 | µA | |||
IL | P-channel current limit | 2.5 V< VI(MAIN) < 6.0 V | 1.4 | 1.75 | 2.1 | A | |
fS | Oscillator frequency | 1 | 1.25 | 1.5 | MHz | ||
VO(MAIN) | Fixed output voltage | 2.5 V | VI(MAIN) = 2.7 V to 6.0 V; IO= 0 mA | 0% | 3% | ||
VI(MAIN) = 2.7 V to 6.0 V; 0 mA ≤ IO≤ 1000 mA |
3% | 3% | |||||
2.75 V | VI(MAIN) = 2.95 V to 6.0 V; IO= 0 mA | 0% | 3% | ||||
VI(MAIN) = 2.95 V to 6.0 V; 0 mA ≤ IO≤ 1000 mA |
3% | 3% | |||||
3.0 V | VI(MAIN) = 3.2 V to 6.0 V; IO= 0 mA | 0% | 3% | ||||
VI(MAIN) = 3.2 V to 6.0 V; 0 mA ≤ IO≤ 1000 mA |
3% | 3% | |||||
3.3 V | VI(MAIN) = 3.5 V to 6.0 V; IO= 0 mA | 0% | 3% | ||||
VI(MAIN) = 3.5 V to 6.0 V; 0 mA ≤ IO≤ 1000 mA |
3% | 3% | |||||
Line regulation | VI(MAIN) = VO(MAIN) + 0.5 V (min. 2.5 V) to 6.0 V, IO = 10 mA |
0.5 | %/V | ||||
Load regulation | IO = 10 mA to 1000 mA | 0.12 | %/A | ||||
R(VMAIN) | VMAIN discharge resistance | 400 | Ω | ||||
VCORE STEP-DOWN CONVERTER | |||||||
VI | Input voltage range | 2.5 | 6.0 | V | |||
IO | Maximum output current | 400 | mA | ||||
IO(SD) | Shutdown supply current | BATT_COVER = GND | 0.1 | 1 | µA | ||
rDS(on) | P-channel MOSFET on-resistance | VI(CORE) = VGS = 3.6 V | 275 | 530 | mΩ | ||
Ilkg(p) | P-channel leakage current | VDS = 6.0 V | 0.1 | 1 | µA | ||
rDS(on) | N-channel MOSFET on-resistance | VI(CORE) = VGS = 3.6 V | 275 | 500 | mΩ | ||
Ilkg(N) | N-channel leakage current | VDS = 6.0 V | 0.1 | 1 | µA | ||
IL | P-channel current limit | 2.5 V< VI(CORE) < 6.0 V | 600 | 700 | 900 | mA | |
fS | Oscillator frequency | 1 | 1.25 | 1.5 | MHz | ||
VO(CORE) | Fixed output voltage | 0.85 V | VI(CORE) = 2.5 V to 6.0 V; IO= 0 mA, CO= 22 µF |
0% | 3% | ||
VI(CORE) = 2.5 V to 6.0 V; 0 mA ≤ IO≤ 400 mA, CO= 22 µF |
3% | 3% | |||||
1.0 V | VI(CORE) = 2.5 V to 6.0 V; IO= 0 mA, CO= 22 µF |
0% | 3% | ||||
VI(CORE) = 2.5 V to 6.0 V; 0 mA ≤ IO≤ 400 mA, CO= 22 µF |
3% | 3% | |||||
1.1 V | VI(CORE) = 2.5 V to 6.0 V; IO= 0 mA, CO= 22 µF |
0% | 3% | ||||
VI(CORE) = 2.5 V to 6.0 V; 0 mA ≤ IO≤ 400 mA, CO= 22 µF |
3% | 3% | |||||
1.2 V | VI(CORE) = 2.5 V to 6.0 V; IO= 0 mA | 0% | 3% | ||||
VI(CORE) = 2.5 V to 6.0 V; 0 mA ≤ IO≤ 400 mA | 3% | 3% | |||||
1.3 V | VI(CORE) = 2.5 V to 6.0 V; IO= 0 mA | 0% | 3% | ||||
VI(CORE) = 2.5 V to 6.0 V; 0 mA ≤ IO≤ 400 mA |
3% | 3% | |||||
1.4 V | VI(CORE) = 2.5 V to 6.0 V; IO= 0 mA | 0% | 3% | ||||
VI(CORE) = 2.5 V to 6.0 V; 0 mA ≤ IO≤ 400 mA |
3% | 3% | |||||
1.5 V | VI(CORE) = 2.5 V to 6.0 V; IO= 0 mA | 0% | 3% | ||||
VI(CORE) = 2.5 V to 6.0 V; 0 mA ≤ IO≤ 400 mA |
3% | 3% | |||||
1.8 V | VI(CORE) = 2.5 V to 6.0 V; IO= 0 mA | 0% | 3% | ||||
VI(CORE) = 2.5 V to 6.0 V; 0 mA ≤ IO≤ 400 mA |
3% | 3% | |||||
Line regulation | VI(CORE) = VO(MAIN) + 0.5 V (min. 2.5 V) to 6.00 V, IO = 10 mA |
1 | %/V | ||||
Load regulation | IO = 10 mA to 400 mA | 0.002 | %/mA | ||||
R(VCORE) | VCORE discharge resistance | 400 | Ω | ||||
VLDO1 and VLDO2 LOW-DROPOUT REGULATORS | |||||||
VI | Input voltage range | LD01 | 1.8 | 6.5 | V | ||
LD02 | 1.8 | VCC | |||||
VO | LDO1 output voltage range | 0.9 | VINLDO1 | V | |||
Vref | Reference voltage | 485 | 500 | 515 | mV | ||
VO | LDO2 output voltage range | 1.8 | 3.3 | V | |||
IO | Maximum output current | Full-power mode | 200 | mA | |||
Low-power mode | 30 | ||||||
I(SC) | LDO1 & LDO2 short-circuit current limit | VLDO1 = GND, VLDO2 = GND | 650 | mA | |||
Dropout voltage | IO= 200 mA, VINLDO1,2 = 1.8 V | 300 | mV | ||||
Total accuracy | ±3% | ||||||
Line regulation | VINLDO1,2 = VLDO1,2 + 0.5 V (min. 2.5 V) to 6.5 V, IO = 10 mA |
0.75 | %/V | ||||
Load regulation | IO = 10 mA to 200 mA | 0.011 | %/mA | ||||
Regulation time | Load change from 10% to 90% | 0.1 | ms | ||||
Low-power mode | 0.1 | ||||||
I(QFP) | LDO quiescent current (each LDO) | Full-power mode | 16 | 30 | µA | ||
I(QLPM) | LDO quiescent current (each LDO) | Low-power mode | 12 | 18 | µA | ||
IO(SD) | LDO shutdown current (each LDO) | 0.1 | 1 | µA | |||
Ilkg(FB) | Leakage current feedback | 0.01 | 0.1 | µA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
V(AC) | Input voltage range | 4.5 | 5.5 | V | |||
V(USB) | Input voltage range | 4.35 | 5.25 | V | |||
ICC(VCHG) | Supply current | V(CHG) > V(CHG)min | 1.2 | 2 | mA | ||
ICC(SLP) | Sleep current | Sum of currents into VBAT pin, V(CHG) < V(SLP-ENTRY), 0°C≤ TJ ≤ 85°C |
2 | 5 | µA | ||
ICC(STBY) | Standby current | Current into USB pin | 45 | µA | |||
Current into AC pin | 200 | 400 | µA | ||||
VOLTAGE REGULATOR | |||||||
VO | Output voltage | V(CHG)min ≥ 4.5 V | 4.15 | 4.20 | 4.25 | V | |
VDO | Dropout voltage (V(AC) - VBAT) | VO(REG) + V(DO-MAX) ≤ V(CHG), IO(OUT) = 1 A |
500 | 800 | mV | ||
Dropout voltage (V(USB) - VBAT) | VO(REG) + V(DO-MAX)≤ V(CHG), IO(OUT) = 0.5 A |
300 | 500 | mV | |||
Dropout voltage (V(USB) - VBAT) | VO(REG) + V(DO-MAX) ≤ V(CHG), IO(OUT) = 0.1 A |
100 | 150 | mV | |||
CURRENT REGULATION | |||||||
IO(AC) | Output current range for AC operation(1) | VCHG ≥ 4.5V, VI(OUT) > V(LOWV), V(AC) - VI(BAT)> V(DO-MAX) |
100 | 1000 | mA | ||
V(SET) | Output current set voltage for AC operation at ISET pin. 100% output current I2C register CHGCONFIG<4:3> = 11 | Vmin ≥ 4.5V, VI(BAT) > V(LOWV), V(AC) - VI(BAT) > V(DO-MAX) | 2.45 | 2.50 | 2.55 | V | |
75% output current I2C register CHGCONFIG<4:3> = 10 | 1.83 | 1.91 | 1.99 | V | |||
50% output current I2C register CHGCONFIG<4:3> = 01 | 1.23 | 1.31 | 1.39 | V | |||
32% output current I2C register CHGCONFIG<4:3> = 00 | 0.76 | 0.81 | 0.86 | V | |||
KSET | Output current set factor for AC operation | 100 mA < IO < 1000 mA | 310 | 330 | 350 | ||
10 mA < IO < 100 mA | 300 | 340 | 380 | ||||
IO(USB) | Output current range for USB operation | V(CHG)min ≥ 4.35 V, VI(BAT) > V(LOWV), V(USB) - VI(BAT)> V(DO-MAX),
I2C register CHGCONFIG<2> = 0 |
80 | 100 | mA | ||
V(CHG)min ≥ 4.5 V, VI(BAT) > V(LOWV), VUSB - VI(BAT) > V(DO-MAX),
I2C register CHGCONFIG<2> = 1 |
400 | 500 | mA | ||||
R(ISET) | Resistor range at ISET pin | 825 | 8250 | Ω | |||
PRECHARGE CURRENT REGULATION, SHORT-CIRCUIT CURRENT, AND BATTERY DETECTION CURRENT | |||||||
V(LOWV) | Precharge to fast-charge transition threshold, voltage on VBAT pin. |
V(CHG)min ≥ 4.5V | 2.8 | 3.0 | 3.2 | V | |
De-glitch time | V(CHG)min ≥ 4.5 V, VI(OUT) decreasing below threshold; 100-ns fall time, 10-mV overdrive | 8.8 | 23 | 60 | ms | ||
I(PRECHG) | Precharge current (2) | 0 ≤ VI(OUT) < V(LOWV), t < t(PRECHG) | 10 | 100 | mA | ||
I(DETECT) | Battery detection current | 200 | µA | ||||
V(SET-PRECHG) | Voltage at ISET pin | 0 ≤ VI(OUT) < V(LOWV), t < t(PRECHG) | 240 | 255 | 270 | mV | |
CHARGE TAPER AND TERMINATION DETECTION | |||||||
I(TAPER) | Taper current detect range (3) | VI(OUT) > V(RCH), t < t(TAPER) | 10 | 100 | mA | ||
V(SET_TAPER) | Voltage at ISET pin for charge TAPER detection | VI(OUT) > V(RCH), t < t(TAPER) | 235 | 250 | 265 | mV | |
V(SET_TERM) | Voltage at ISET pin for charger termination detection(4) |
VI(OUT) > V(RCH) | 11 | 18 | 25 | mV | |
De-glitch time for I(TAPER) | V(CHG)min ≥ 4.5V, charging current increasing or decreasing above and below; 100-ns fall time, 10-mV overdrive |
8.8 | 23 | 60 | ms | ||
De-glitch time for I(TERM) | V(CHG)min ≥ 4.5 V, charging current decreasing below;100-ns fall time, 10-mV overdrive | 8.8 | 23 | 60 | ms | ||
TEMPERATURE COMPARATOR | |||||||
V(LTF) | Low (cold) temperature threshold | 2.475 | 2.50 | 2.525 | V | ||
V(HTF) | High (hot) temperature threshold | 0.485 | 0.5 | 0.515 | V | ||
I(TS) | TS current source | 95 | 102 | 110 | µA | ||
De-glitch time for temperature fault | 8.8 | 23 | 60 | ms | |||
BATTERY RECHARGE THRESHOLD | |||||||
V(RCH) | Recharge threshold | V(CHG)min≥ 4.5 V | VO(REG) -0.115 | VO(REG) -0.1 | VO(REG) -0.085 | V | |
De-glitch time | V(CHG)min ≥ 4.5 V, VI(OUT) decreasing below threshold; 100-ns fall time, 10-mV overdrive |
8.8 | 23 | 60 | ms | ||
TIMERS | |||||||
t(PRECHG) | Precharge timer | V(CHG)min ≥ 4.5 V | 1500 | 1800 | 2160 | s | |
t(TAPER) | Taper timer | V(CHG)min≥ 4.5 V | 1500 | 1800 | 2160 | s | |
t(CHG) | Charge timer | V(CHG)min≥ 4.5 V | 15000 | 18000 | 21600 | s | |
SLEEP AND STANDBY | |||||||
V(SLP-ENTRY) | Sleep-mode entry threshold, PG output = high | 2.3 V≤ VI(OUT) ≤ VO(REG) | V(CHG)≤ VI(OUT) +150 mV | V | |||
V(SLP_EXIT) | Sleep-mode exit threshold,PG output = low | 2.3 V≤ VI(OUT)≤ VO(REG) | V(CHG)≥ VI(OUT)+190 mV | V | |||
De-glitch time for sleep mode entry and exit | AC or USB decreasing below threshold; 100-ns fall time, 10-mV overdrive | 8.8 | 23 | 60 | ms | ||
t(USB_DEL) | Delay between valid USB voltage being applied and start of charging process from USB | 5 | ms | ||||
CHARGER POWER-ON-RESET, UVLO, AND V(IN) RAMP RATE | |||||||
V(CHGUVLO) | Charger undervoltage lockout | V(CHG) decreasing | 2.27 | 2.5 | 2.75 | V | |
Hysteresis | 27 | mV | |||||
V(CHGOVLO) | Charger overvoltage lockout | V(AC) increasing | 6.6 | V | |||
Hysteresis | 0.5 | V | |||||
CHARGER OVERTEMPERATURE SUSPEND | |||||||
T(suspend) | Temperature at which charger suspends operation |
145 | °C | ||||
T(hyst) | Hysteresis of suspend threshold | 20 | °C | ||||
LOGIC SIGNALS DEFMAIN, DEFCORE, PS_SEQ, IFLSB | |||||||
VIH | High level input voltage | IIH = 20 µA | VCC-0.5 | VCC | V | ||
VIL | Low level input voltage | IIL = 10 µA | 0 | 0.4 | V | ||
IIB | Input bias current | 0.01 | 1.0 | µA | |||
LOGIC SIGNALS GPIO1-4 | |||||||
VOL | Low level output voltage | IOL = 1 mA, configured as an open-drain output |
0.3 | V | |||
VOH | High level output voltage | Configured as an open-drain output | 6 | V | |||
VIL | Low level input voltage | 0 | 0.8 | V | |||
VIH | High level input voltage | 2 | VCC (5) | V | |||
II | Input leakage current | 1 | µA | ||||
rDS(on) | Internal NMOS | VOL = 0.3 V | 150 | Ω | |||
LOGIC SIGNALS PG, LED2 | |||||||
VOL | Low level output voltage | IOL = 20 mA | 0.5 | V | |||
VOH | High level output voltage | 6 | V | ||||
VIBRATOR DRIVER VIB | |||||||
VOL | Low level output voltage | IOL = 100 mA | 0.3 | 0.5 | V | ||
VOH | High level output voltage | 6 | V | ||||
THERMAL SHUTDOWN | |||||||
T(SD) | Thermal shutdown | Increasing junction temperature | 160 | °C | |||
UNDERVOLTAGE LOCKOUT | |||||||
V(UVLO) | Undervoltage lockout threshold. The default value for UVLO is 2.75 V |
V(UVLO) 2.5 V | Filter resistor = 10R in series with VCC, VCC decreasing |
-3% | 3% | ||
V(UVLO) 2.75 V | -3% | 3% | |||||
V(UVLO) 3.0 V | -3% | 3% | |||||
V(UVLO) 3.25 V | -3% | 3% | |||||
V(UVLO_HYST) | UVLO comparator hysteresis | VCC rising | 350 | 400 | 450 | mV | |
POWER GOOD | |||||||
VMAIN, VCORE, VLDO1, VLDO2 decreasing |
-12% | -10% | -8% | ||||
VMAIN, VCORE, VLDO1, VLDO2 increasing |
-7% | -5% | -3% |
MIN | MAX | UNIT | ||
---|---|---|---|---|
fMAX | Clock frequency | 400 | kHz | |
twH(HIGH) | Clock high time | 600 | ns | |
twL(LOW) | Clock low time | 1300 | ns | |
tR | DATA and CLK rise time | 300 | ns | |
tF | DATA and CLK fall time | 300 | ns | |
th(STA) | Hold time (repeated) START condition (after this period the first clock pulse is generated) | 600 | ns | |
th(DATA) | Setup time for repeated START condition | 600 | ns | |
th(DATA) | Data input hold time | 0 | ns | |
tsu(DATA) | Data input setup time | 100 | ns | |
tsu(STO) | STOP condition setup time | 600 | ns | |
t(BUF) | Bus free time | 1300 | ns |
AMBIENT TEMPERATURE |
MAX POWER DISSIPATION FOR TJ= 125°C(2) |
DERATING FACTOR ABOVE TA= 55°C |
---|---|---|
25°C | 3 W | 30 mW/°C |
55°C | 2.1 W | 30 mW/°C |
FIGURE | ||
---|---|---|
Efficiency | vs Output current | Figure 1, Figure 2, Figure 3, Figure 4 |
Quiescent current | vs Input voltage | Figure 5 |
Switching frequency | vs Temperature | Figure 6 |
Output voltage | vs Output current | Figure 7, Figure 8 |
LDO1 Output voltage | vs Output current | Figure 9 |
LDO2 Output voltage | vs Output current | Figure 10 |
Line transient response (main) | Figure 11 | |
Line transient response (core) | Figure 12 | |
Line transient response (LDO1) | Figure 13 | |
Line transient response (LDO2) | Figure 14 | |
Load transient response (main) | Figure 15 | |
Load transient response (core) | Figure 16 | |
Load transient response (LDO1) | Figure 17 | |
Load transient response (LDO2) | Figure 18 | |
Output Voltage Ripple (PFM) | Figure 19 | |
Output Voltage Ripple (PWM) | Figure 20 | |
Start-up timing | Figure 21 | |
Dropout voltage | vs Output current | Figure 22, Figure 23 |
PSRR (LDO1 and LDO2) | vs Frequency | Figure 24 |
The TPS65011 charger automatically selects the USB-Port or the AC-adapter as the power source for the system. In the USB configuration, the host can increase the charge current from the default value of maximum 100 mA to 500 mA via the interface. In the AC-adapter configuration, an external resistor sets the maximum value of charge current.
The battery is charged in three phases: conditioning, constant current, and constant voltage. Charge is normally terminated based on minimum current. An internal charge timer provides a safety backup for charge termination. The TPS65011 automatically restarts the charge if the battery voltage falls below an internal threshold. The charger automatically enters sleep mode when both supplies are removed.
The serial interface can be used for dynamic voltage scaling, for collecting information on and controlling the battery charger status, for optionally controlling 2 LED driver outputs, a vibrator driver, masking interrupts, or for disabling/enabling and setting the LDO output voltages. The interface is compatible with the fast/standard mode specification allowing transfers at up to 400 kHz.
Battery Charger, Step-Down Converters, LDOs, UVLO protection, Rail Sequencing, Vibrator Driver, and various logic level controls. The LOW_PWR pin allows the core converter to lower its output voltage when the application processor goes into deep sleep.
The TPS65011 supports a precision Li-Ion or Li-Polymer charging system suitable for single cells with either coke or graphite anodes. Charging the battery is possible even without the application processor being powered up. The TPS65011 starts charging when an input voltage on either AC or USB input is present, which is greater than the charger UVLO threshold. See Figure 25 for a typical charge profile.
Per default the TPS65011 attempts to charge from the AC input. If AC input is not present, the USB is selected. If both inputs are available, the AC input has priority. The charge current is initially limited to 100 mA when charging from the USB input. This can be increased to 500 mA via the serial interface. The charger can be completely disabled via the interface, and it is also possible just to disable charging from the USB port. The start of the charging process from the USB port is delayed in order to allow the application processor time to disable USB charging, for instance if a USB OTG port is recognized. The recommended input voltage for charging from the AC input is 4.5 V < VAC < 5.5 V. However, the TPS65011 is capable of withstanding (but not charging from) up to 20 V. Charging is disabled if VAC is greater than typically 6.6 V.
The TPS65011 continuously monitors battery temperature by measuring the voltage between the TS and AGND pins. An internal current source provides the bias for most common 10K negative-temperature coefficient thermistors (NTC) (see Figure 26). The IC compares the voltage on the TS pin against the internal V(LTF) and V(HTF) thresholds to determine if charging is allowed. Once a temperature outside the V(LTF) and V(HTF) thresholds is detected, the IC immediately suspends the charge. The IC suspends charge by turning off the power FET and holding the timer value (i.e., timers are not reset). Charge is resumed when the temperature returns to the normal range.
The allowed temperature range for 103-A T-type thermistor is 0°C to 45°C. However, the user may modify these thresholds by adding two external resistors. See Figure 27.
On power up, if the battery voltage is below the V(LOWV) threshold, the TPS65011 applies a precharge current, I(PRECHG), to the battery. This feature revives deeply discharged cells. The charge current during this phase is one tenth of the value in current regulation phase which is set with IO(out) = KSET × V(SET)/R(SET). The load current in preconditioning phase must be lower than I(PRECHG) and must allow the battery voltage to rise above V(LOWV) within t(Prechg). VBAT_A is the sense pin to the voltage comparator for the battery voltage. This allows a power-on sense measurement if the VBAT_A and VBAT_B pins are connected together at the battery.
The TPS65011 activates a safety timer, t(PRECHG), during the conditioning phase. If V(LOWV) threshold is not reached within the timer period, the TPS65011 turns off the charger and indicates the fault condition in the CHGSTATUS register. In the case of a fault condition, the TPS65011 reduces the current to I(DETECT). I(DETECT)is used to detect a battery replacement condition. Fault condition is cleared by POR or battery replacement or via the serial interface.
TPS65011 offers on-chip current regulation. When charging from an AC adapter, a resistor connected between the ISET1 and AGND pins determines the charge rate. A maximum of 1-A charger current from the AC adapter is allowed. When charging from a USB port either a 100-mA or 500-mA charge rate can be selected via the serial interface, default is 100 mA maximum. Two bits are available in the CHGCONFIG register in the serial interface to reduce the charge current in 25% steps. These only influence charging from the AC input and may be of use if charging is often suspended due to excessive junction temperature in the TPS65011 ( essentially at high AC input voltages) and low battery voltages.
The voltage regulation feedback is through the VBAT pin. This pin is tied directly to the positive side of the battery pack. The TPS65011 monitors the battery-pack voltage between the VBAT and AGND pins. The TPS65011 is offered in a fixed-voltage version of 4.2 V.
As a safety backup, the TPS65011 also monitors the charge time in the fast-charge mode. If taper current is not detected within this time period, t(CHG), the TPS65011 turns off the charger and indicates FAULT in the CHGSTATUS register. In the case of a FAULT condition, the TPS65011 reduces the current to I(DETECT). I(DETECT) is used to detect a battery replacement condition. Fault condition is cleared by POR via the serial interface. Note that the safety timer is reset if the TPS65011 is forced out of the voltage regulation mode. The fast-charge timer is disabled by default to allow charging during normal operation of the end equipment. It is enabled via the CHGCONFIG register.
The TPS65011 monitors the charging current during the voltage regulation phase. Once the taper threshold, I(TAPER), is detected, the TPS65011 initiates the taper timer, t(TAPER). Charge is terminated after the timer expires. The TPS65011 resets the taper timer in the event that the charge current returns above the taper threshold, I(TAPER). After a charge termination, the TPS65011 restarts the charge once the voltage on the VBAT pin falls below the V(RCH) threshold. This feature keeps the battery at full capacity at all times. The fast charge timer and the taper timer must be enabled by programming CHGCONFIG(5)=1. A thermal suspend will suspend the fast-charge and taper timers.
In addition to the taper current detection, the TPS65011 terminates charge in the event that the charge current falls below the I(TERM) threshold. This feature allows for quick recognition of a battery removal condition. When a full battery is replaced with an empty battery, the TPS65011 detects that the VBAT voltage is below the recharge threshold and starts charging the new battery. The taper and termination bits are cleared in the CHGSTATUS register and if the INT pin is still active due to these two interrupt sources, then it is de-asserted. Depending on the transient seen at the VCC pin, all registers may be set to their default values and require reprogramming with any nondefault values required, such as enabling the fast-charge timer and taper termination; this should only happen if VCC drops below approximately 2 V.
The TPS65011 charger enters the low-power sleep mode if both input sources are removed from the circuit. This feature prevents draining the battery during the absence of input power.
The open-drain, power-good (PG) output indicates when a valid power supply is present for the charger. This can be either from the AC adapter input or from the USB. The output turns ON when a valid voltage is detected. A valid voltage is detected whenever the voltage on either pin AC or pin USB rises above the voltage on VBAT plus 100 mV. This output is turned off in the sleep mode. The PG pin can be used to drive an LED or communicate to the host processor. A voltage greater than the V(CHGOVLO) threshold (typ 6.6 V) at the AC input is not valid and does not activate the PG output. The PG output is held in high impedance state if the charger is in reset by programming CHGCONFIG(6)=1.
The PG output can also be programmed via the LED1_ON and LED1_PER registers in the serial interface. It can then be programmed to be permanently on, off, or to blink with defined on- and period-times. PG is controlled per default via the charger.
The TPS65011 is housed in a 48-pin QFN package with exposed leadframe on the underside. This 7 mm × 7 mm package exhibits a thermal impedance (junction-to-ambient) of 33 K/W when mounted on a JEDEC high-k board with zero air flow.
AMBIENT TEMPERATURE | MAX POWER DISSIPATION FOR TJ= 125°C | DERATING FACTOR ABOVE TA= 55°C |
---|---|---|
25°C | 3 W | 30 mW/°C |
55°C | 2.1 W |
Consideration needs to be given to the maximum charge current when the assembled application board exhibits a thermal impedance, which differs significantly from the JEDEC high-k board. The charger has a thermal shutdown feature, which suspends charging if the TPS65011 junction temperature rises above a threshold of 145°C. This threshold is set 15°C below the threshold used to power down the TPS65011 completely.
The TPS65011 incorporates two synchronous step-down converters operating typically at 1.25 MHz fixed frequency pulse width modulation (PWM) at moderate to heavy load currents. At light load currents, the converters automatically enter power save mode and operate with pulse frequency modulation (PFM). The main converter is capable of delivering 1-A output current and the core converter is capable of delivering 400 mA.
The converter output voltages are programmed via the VDCDC1 and VDCDC2 registers in the serial interface. The main converter defaults to 3.0-V or 3.3-V output voltage depending on the DEFMAIN configuration pin, if DEFMAIN is tied to ground, the default is 3.0 V; if it is tied to VCC, the default is 3.3 V. The core converter defaults to either 1.5 V or 1.8 V depending on whether the DEFCORE configuration pin is tied to GND or to VCC, respectively. Both the main and core output voltages can subsequently be reprogrammed after start-up via the serial interface. In addition, the LOW_PWR pin can be used either to lower the core voltage to a value defined in the VDCDC2 register when the application processor is in deep sleep mode or to disable the core converter. An active signal at LOW_PWR is ignored if the ENABLE_LP bit is not set in the VDCDC1 register.
The step-down converter outputs (when enabled) are monitored by power-good comparators, the outputs of which are available via the serial interface. The outputs of the DC-DC converters can be optionally discharged when the DC-DC converters are disabled.
During PWM operation, the converters use a unique fast response voltage mode controller scheme with input voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output capacitors. At the beginning of each clock cycle, initiated by the clock signal, the P-channel MOSFET switch is turned on, and the inductor current ramps up until the comparator trips and the control logic turns off the switch. The current limit comparator also turns off the switch in case the current limit of the P-channel switch is exceeded. After the dead time preventing current shoot through, the N-channel MOSFET rectifier is turned on and the inductor current ramps down. The next cycle is initiated by the clock signal again turning off the N-channel rectifier and turning on the P-channel switch.
The error amplifier, together with the input voltage, determines the rise time of the saw-tooth generator, and therefore, any change in input voltage or output voltage directly controls the duty cycle of the converter giving a good line and load transient regulation.
The two DC-DC converters operate synchronized to each other, with the MAIN converter as the master. A 270° phase shift between the MAIN switch turn on and the CORE switch turn on decreases the input RMS current, and smaller input capacitors can be used. This is optimized for a typical application where the MAIN converter regulates a Li-Ion battery voltage of 3.7 V to 3.3 V and the CORE from 3.7 V to 1.5 V.
As the load current decreases, the converter enters the power save mode operation. During power save mode, the converter operates with reduced switching frequency in PFM mode and with a minimum quiescent current to maintain high efficiency.
In order to optimize the converter efficiency at light load, the average current is monitored; if in PWM mode, the inductor current remains below a certain threshold, and then power save mode is entered. The typical threshold can be calculated with Equation 1:
During the power save mode the output voltage is monitored with the comparator by the thresholds comp low and comp high. As the output voltage falls below the comp low threshold, set to typically 0.8% above the nominal Vout, the P-channel switch turns on. The converter then runs at 50% of the nominal switching frequency. If the load is below the delivered current, then the output voltage rises until the comp high threshold is reached, typically 1.6% above the nominal Vout. At this point, all switching activity ceases, hence reducing the quiescent current to a minimum until the output voltage has dropped below comp low again. If the load current is greater than the delivered current, then the output voltage falls until it crosses the nominal output voltage threshold (comp low 2 threshold), whereupon power save mode is exited, and the converter returns to PWM mode.
These control methods reduce the quiescent current typically to 12-µA per converter and the switching frequency to a minimum, achieving the highest converter efficiency. Setting the comparator thresholds to typically 0.8% and 1.6% above the nominal output voltage at light load current results in a dynamic voltage positioning achieving lower absolute voltage drops during heavy load transient changes. This allows the converters to operate with a small output capacitor of just 10 µF for the core and 22 µF for the main output and still have a low absolute voltage drop during heavy load transient changes. See Figure 28 for detailed operation of the power save mode. The power save mode can be disabled through the I2C interface to force the converters to stay in fixed frequency PWM mode.
The core and main converters are forced into PWM mode by setting bit 7 in the VDCDC1 register. This feature is used to minimize ripple on the output voltages.
As described in the Power Save Mode Operation sections and as detailed in Figure 13, the output voltage is typically 1.2% above the nominal output voltage at light load currents as the device is in power save mode. This gives additional headroom for the voltage drop during a load transient from light load to full load. During a load transient from full load to light load, the voltage overshoot is also minimized due to active regulation turning on the N-channel rectifier switch.
Both converters have an internal soft start circuit that limits the inrush current during start-up. The soft start is implemented as a digital circuit increasing the switch current in 4 steps up to the typical maximum switch current limit of 700 mA (core) and 1.75 A (main). Therefore, the start-up time mainly depends on the output capacitor and load current.
The TPS65011 converters offer a low input to output voltage difference while maintaining operation with the use of the 100% duty cycle mode. In this mode, the P-channel switch is constantly turned on. This is particularly useful in battery-powered applications to achieve longest operation time by taking full advantage of the whole battery voltage range. The minimum input voltage to maintain regulation depends on the load current and output voltage and is calculated as:
with:
When the CORE and MAIN converters are disabled, due to an UVLO, BATT_COVER or OVERTEMP condition, it is possible to actively pull down the outputs. This feature is disabled per default and is individually enabled via the VDCDC1 and VDCDC2 registers in the serial interface. When this feature is enabled, the core and main outputs are discharged by a 400-Ω (typical) load.
Both the MAIN and CORE converters have power-good comparators. Each comparator indicates when the relevant output voltage has dropped 10% below its target value, with 5% hysteresis. The outputs of these comparators are available in the REGSTATUS register via the serial interface. A maskable interrupt is generated when any voltage rail drops below the 10% threshold. The comparators are disabled when the converters are disabled. The status of the power-good comparator for VMAIN is used to generate the RESPWRON signal.
The MAIN and CORE converters are automatically shut down if the temperature exceeds the trip point (see the electrical characteristics). This detection is only active if the converters are in PWM mode, either by setting FPWM = 1, or if the output current is high enough that the device runs in PWM mode automatically.
The low-dropout voltage regulators are designed to operate with low value ceramic input and output capacitors. They operate with input voltages down to 1.8 V. The LDOs offer a maximum dropout voltage of 300 mV at rated output current. Each LDO has a current limit feature. Both LDOs are enabled per default; both LDOs can be disabled or programmed via the serial interface using the VREGS1 register. The LDO outputs (when enabled) are monitored by power-good comparators, the outputs of which are available via the serial interface. The LDOs also have reverse conduction prevention when disabled. This allows the possibility to connect external regulators in parallel in systems with a backup battery.
Both the LDO1 and LDO2 linear regulators have power-good comparators. Each comparator indicates when the relevant output voltage has dropped 10% below its target value, with 5% hysteresis. The outputs of these comparators are available in the REGSTATUS register via the serial interface. An interrupt is generated when any voltage rail drops below the 10% threshold. The LDO2 comparator is disabled when LDO2 is disabled.
Enabling and sequencing of the DC-DC converters and LDOs are described in the Power-Up Sequencing section. The OMAP1510 processor from Texas Instruments requires that the core power supply is enabled before the I/O power supply, which means that the CORE converter should power up before the MAIN converter. This is achieved by connecting PS_SEQ to GND.
The undervoltage lockout circuit for the four regulators on TPS65011 prevents the device from malfunctioning at low input voltages and from excessive discharge of the battery. Basically, it prevents the converter from turning on the power switch or rectifier FET under undefined conditions. The undervoltage threshold voltage is set by default to 2.75 V. After power-up, the threshold voltage can be reprogrammed through the serial interface. The undervoltage lockout comparator compares the voltage on the VCC pin with the UVLO threshold. When the VCC voltage drops below this threshold, the TPS65011 sets the PWRFAIL pin low and after a time t(UVLO) disables the voltage regulators in the sequence defined by PS_SEQ. The same procedure is followed when the TPS65011 detects that its junction temperature has exceeded the overtemperature threshold, typically 160°C, with a delay t(overtemp). The TPS65011 automatically restarts when the UVLO (or overtemperature) condition is no longer present.
The battery charger circuit has a separate UVLO circuit with a threshold of typically 2.5 V, which is compared with the voltage on AC and USB supply pins.
The TPS65011 power-up sequencing is designed to allow the maximum flexibility without generating excessive logistical or system complexity. The relevant control pins are described in the following table:
PIN NAME | INPUT OR OUTPUT | FUNCTION |
---|---|---|
PS_SEQ | I | Input signal indicating power up and down sequence of the switching converters. PS_SEQ = 0 forces the core regulator to ramp up first and down last. PS_SEQ = 1 forces the main regulator to ramp up first and down last. |
DEFCORE | I | Defines the default voltage of the VCORE switching converter. DEFCORE = 0 defaults VCORE to 1.5 V, DEFCORE = VCC defaults VCORE to 1.8 V. |
DEFMAIN | I | Defines the default voltage of the VMAIN switching converter. DEFMAIN = 0 defaults VMAIN to 3.0 V, DEFMAIN = VCC defaults VMAIN to 3.3 V. |
LOW_PWR | I | The LOW_PWR pin is used to lower VCORE to the preset voltage in the VDCDC2 register when the processor is in deep sleep mode. Alternatively VCORE can be disabled in low-power mode if the LP_COREOFF bit is set in the VDCDC2 register. LOW_PWR is ignored if the ENABLE LP bit is not set in the VDCDC1 register. The TPS65011 uses the rising edge of the internal signal formed by a logical AND of LOW_PWR and ENABLE LP to enter low-power mode. TPS65011 is forced out of low-power mode by de-asserting LOW_PWR, by resetting ENABLE LP to 0, by activating the PB_ONOFF pin or by activating the HOT_RESET pin. There are two ways to get the device back into low-power mode: a) toggle the LOW_PWR pin, or b) toggle the low-power bit when the LOW_PWR pin is held high. The LOW_PWR pin is also used to set the TPS65011 into WAIT mode. If USB or AC is present, the AUA bit (CHCONFIG<7>) must be set to enter the WAIT mode, see Figure 29. |
PB_ONOFF | I | PB_ONOFF can be used to exit the low-power mode and return the core voltage to the value before low-power mode was entered. If PB_ONOFF is used to exit the low-power mode, then the low-power mode can be reentered by toggling the LOW_PWR pin or by toggling the low-power bit when the LOW_PWR pin is held high. A 1-MΩ pulldown resistor is integrated in TPS65011. PB_ONOFF is internally de-bounced by the TPS65011. A maskable interrupt is generated when PB_ONOFF is activated. |
HOT_RESET | I | The HOT_RESET pin has a very similar functionality to the PB_ONOFF pin. In addition it generates a reset (MPU_RESET) for the MPU when the VCORE voltage is in regulation. HOT_RESET does not alter any TPS65011 settings unless low-power mode was active in which case it is exited. A 1-MΩ pullup resistor to VCC is integrated in TPS65011. HOT_RESET is internally de-bounced by the TPS65011. |
BATT_COVER | I | The BATT_COVER pin is used as an early warning that the main battery is about to be removed. BATT_COVER = VCC indicates that the cover is in place, BATT_COVER = 0 indicates that the cover is not in place. TPS65011 generates a maskable interrupt when the BATT_COVER pin goes low. PWRFAIL is also held low when BATT_COVER goes low. This feature may be disabled by tying BATT_COVER permanently to VCC. The TPS65011 shuts down the main and the core converter and sets the LDOs into low-power mode. A 2-MΩ pulldown resistor is integrated in the TPS65011 at the BATT_COVER pin. BATT_COVER is internally de-bounced by the TPS65011. |
RESPWRON | O | RESPWRON is held low while the switching converters (and any LDO's defined as default on) are starting up. It is determined by the state of MAIN's output voltage; when the voltage is higher than the power-good comparator threshold then RESPWRON is high, when VMAIN is low then RESPWRON is low. RESPWRON is held low for tn(RESPWRON) sec after VMAIN has settled. |
MPU_RESET | O | MPU_RESET can be used to reset the processor if the user activates the HOT_RESET button. The MPU_RESET output is active for t(MPU_nRESET) sec. It also forces TPS65011 to leave low-power mode. MPU_RESET is also held low as long as RESPWRON is held low. |
PWRFAIL | O | PWRFAIL indicates when VCC < V(UVLO), when the TPS65011 is about to shut down due to an internal overtemperature condition or when BATT_COVER is low. PWRFAIL is also held low as long as RESPWRON is held low. |
TPOR | I | TPOR is used to set the delay time for the RESPWRON reset signal. TPOR = 0 sets the delay time to 100 ms. TPOR = 1 sets the delay time to 1 s. |
Figure 29 shows the state diagram for the TPS65011 power sequencing. The charger function is not shown in the state diagram since this function is independent of these states.
The RESPWRON signal is used as a global reset for the application. It is an open drain output. The RESPWRON signal is generated according to the Power Good comparator linked to VMAIN and remains low for tn(RESPWRON) seconds after VMAIN has stabilized. When RESPWRON is low, PWRFAIL, MPU_RESET and INT are also held low.
If the output voltage of MAIN is less than 90% of its nominal value, as RESPWRON is generated, and if the output voltage of MAIN is programmed to a higher value, which causes the output voltage to fall out of the 90% window, then a RESPWRON signal is generated.
The PWRFAIL signal indicates when VCC < UVLO or when the TPS65011 junction temperature has exceeded a reliable value or if BATT_COVER is taken low. This open drain output can be connected at a fast interrupt pin for immediate attention by the application processor. All supplies are disabled t(uvlo), t(overtemp) or t(batt_cover) seconds after PWRFAIL has gone low, giving time for the application processor to shut down cleanly.
BATT_COVER is used to detect whether the battery cover is in place or not. If the battery cover is removed, the TPS65011 generates a warning to the processor that the battery is likely to be removed and that it may be prudent to shut down the system. If not required, this feature may be disabled by connecting the BATT_COVER pin to the VCC pin. BATT_COVER is de-bounced internally. Typical de-bounce time is 56 ms. BATT_COVER has an internal 2-MΩ pulldown resistor.
The HOT_RESET input is used to generate an MPU_RESET signal for the application processor. The HOT_RESET pin could be connected to a user-activated button in the application. It can also be used to exit low-power mode. In this case, the TPS65011 waits until the VCORE voltage has stabilized before generating the MPU_RESET pulse. The MPU_RESET pulse is active low for t(mpu_nreset) seconds. HOT_RESET has an internal 1-MΩ pullup resistor to VCC.
The PB_ONOFF input can be used to exit low-power MODE. It is typically driven by a user-activated push-button in the application. Both HOT_RESET and PB_ONOFF are de-bounced internally by the TPS65011. Typical de-bounce time is 56 ms. PB_ONOFF has an internal 1-MΩ pulldown resistor.
PB_ONOFF, BATT_COVER and UVLO events also cause a normal, maskable interrupt to be generated and are noted in the REGSTATUS register.
The VIB open-drain output is provided to drive a vibrator motor, controlled via the serial interface register VDCDC2. It has a maximum dropout of 0.5 V at 100-mA load. Typically, an external resistor is required to limit the motor current, and a freewheel diode to limit the VIB overshoot voltage at turnoff.
No batteries are connected to the TPS65011. When main power is applied, the bandgap reference, LDOs, and UVLO comparator start up. The RESPWRON, PWRFAIL, INT and MPU_RESET signals are held low. When BATT_COVER goes high (de-bounced internally by the TPS65011), indicating that the battery cover has been put in place and if VCC > UVLO, the power supplies are ramped in the sequence defined by PS_SEQ. RESPWRON, PWRFAIL, INT and MPU_RESET are released when the RESPWRON timer has timed out after tn(RESPWRON) sec. If VCC remains valid and no OVERTEMP condition occurs, then the TPS65011 arrives in State 2: ON. If VCC < UVLO, the TPS65011 keeps the bandgap reference and UVLO comparator active such that when VCC>UVLO (during battery charge) the supplies are automatically activated.
In this state, TPS65011 is fired up and ready to go. The switching converters can have their output voltages programmed. The LDOs can be disabled or programmed. TPS65011 can exit this state either due to an overtemperature condition, by an undervoltage condition at VCC, by BATT_COVER going low, or by the processor programming low-power mode. State 2 is left temporarily if the user activates the HOT_RESET pin.
This state is entered via the processor setting the ENABLE_LP bit in the serial interface and then raising the LOW_PWR pin. The TPS65011 actually uses the rising edge of the internal signal formed by a logical AND of the LOW_PWR and ENABLE LP signals to enter low-power mode. The VMAIN switching converter remains active, but the VCORE converter may be disabled in low-power mode via the serial interface by setting the LP_COREOFF bit in the VDCDC2 register. If left enabled, the VCORE voltage is set to the value predefined by the CORELP0/1 bits in the VDCDC2 register. The LDO1OFF/nSLP and LDO2OFF/nSLP bits in the VREGS1 register determine whether the LDOs are turned off or put in a reduced power mode (transient speed-up circuitry disabled in order to minimize quiescent current) in low-power mode. All TPS65011 features remain addressable via the serial interface. TPS65011 can exit this state either due to an undervoltage condition at VCC, due to BATT_COVER going low, due to an OVERTEMP condition, by the processor deasserting the LOW_POWER pin, or by the user activating the HOT_RESET pin or the PB_ONOFF pin.
There are two scenarios for entering this state. The first is from State 1: No Power. As soon as main battery power is applied, the device automatically enters the WAIT mode.
The second scenario occurs when the device is in ON mode and the processor initiates a shutdown by resetting the ENABLE SUPPLY bit in the VDCDC1 register (ENABLE_LP must be high), and then raising the LOW_PWR pin. When this happens, the power rails are ramped down in the predefined sequence, and all circuitry is then disabled. In this state, the TPS65011 waits for the PB_ONOFF or HOT_RESET pin to be activated before enabling any of the supply rails. When the PB_ONOFF or HOT_RESET pin is activated, the TPS65011 powers up the supplies according to the same constraints as at the initial application of power. Complete shutdown is only achieved by setting the LDO1OFF/nSLP and LDO2OFF/nSLP bits high in the VREGS1 register before activating the shutdown.
In this case, the I2C interface is deactivated and the registers are reset to their default value after leaving the WAIT mode.
To enter the WAIT mode when USB or AC is present, the AUA bit (CHCONFIG<7>) must be set. The WAIT mode is automatically left if Bit 7 in register CHCONFIG is set to 0 (default), and a voltage is present at either the AC pin or the USB pin in the appropriate range for charging, and the voltage at VCC is above the UVLO threshold. This feature allows the converters to start up automatically if the device is plugged in for charging.
If all supplies are turned off in WAIT mode, the internal bandgap is switched off, and the internal registers are reset to their default state when the device returns to ON mode.
Table 3 shows possible configurations in LOW-POWER mode and WAIT mode.
CONVERTER | MAIN | CORE | LDO1 | LDO2 |
---|---|---|---|---|
LOW POWER mode | 1 | 0/1 | 0/1 | 0/1 |
WAIT mode | 0 | 0 | 0/1 | 0/1 |
Table 4 indicates the typical quiescent current consumption in each power state.
STATE | TOTAL QUIESCENT CURRENT |
QUIESCENT CURRENT BREAKDOWN |
---|---|---|
1 | 0 | |
2 | 30 µA-70 µA | VMAIN (12 µA) + VCORE (12 µA) + LDOs (20 µA each, max 2) + UVLO + reference + PowerGood |
3 | 30 µA-55 µA | VMAIN (12 µA) + VCORE (12 µA) + LDOs (10 µA each, max 2) + UVLO + reference + PowerGood |
4 | 13 µA | UVLO + reference circuitry |
Valid for LDO1 supplied from VMAIN as described in Application Information.
If 2.4 ms after application, VCC is still below the default UVLO threshold (3.15 V for VCC rising), then start up is as shown in Figure 31.
Valid for LDO1 supplied from VMAIN as described in Application Information.
Valid for LDO1 supplied from VMAIN as described in Application Information.
The LED2 output can be programmed in the same way as the PG output to blink or to be permanently on or off. The LED2_ON and LED2_PER registers are used to control the blink rate. For both PG and LED2, the minimum blink-on time is 10 ms and this can be increased in 127 10-ms steps to 1280 ms. For both PG and LED2, the minimum blink period is 100 ms and this can be increased in 127 100-ms steps to 12800 ms.
The open-drain INT pin is used to combine and report all possible conditions via a single pin. Battery and chip temperature faults, precharge timeout, charge timeout, taper timeout, and termination current are each capable of setting INT low, i.e., active. INT can also be activated if any of the regulators are below the regulation threshold. Interrupts can also be generated by any of the GPIO pins programmed to be inputs. These inputs can be programmed to generate an interrupt either at the rising or falling edge of the input signal. It is possible to mask an interrupt from any of these conditions individually by setting the appropriate bits in the MASK1, MASK2, or MASK3 registers. By default, all interrupts are masked. Interrupts are stored in the CHGSTATUS, REGSTATUS, and DEFGPIO registers in the serial interface. CHGSTATUS and REGSTATUS interrupts are acknowledged by reading these registers. If a 1 is present in any location, then the TPS65011 automatically sets the corresponding bit in the ACKINT1 or ACKINT2 registers and releases the INT pin. The ACKINT register contents are self-clearing when the condition, which caused the interrupt, is removed. The applications processor should not normally need to access the ACKINT1 or ACKINT2 registers.
Interrupt events are always captured; thus when an interrupt source is unmasked, INT may immediately go active due to a previous interrupt condition. This can be prevented by first reading the relevant STATUS register before unmasking the interrupt source.
If an interrupt condition occurs, then the INT pin is set low. The CHGSTATUS, REGSTATUS, and DEFGPIO registers should be read. Bit positions containing a 1 (or possibly a 0 in DEFGPIO) are noted by the CPU and the corresponding situation resolved. The reading of the CHGSTATUS and REGSTATUS registers automatically acknowledges any interrupt condition in those registers and blocks the path to the INT pin from the relevant bit(s). No interrupt should be missed during the read process since this process starts by latching the contents of the register before shifting them out at SDAT. Once the contents have been latched (takes a couple of nanoseconds), the register is free to capture new interrupt conditions. Hence, the probability of missing anything is, for practical purposes, zero.
The following describes how registers 0x01 (CHGSTATUS) and 0x02 (REGSTATUS) are handled:
The following describes the function of the 0x05 (ACKINT1) and 0x06 (ACKINT2) registers. These are not usually written to by the CPU since the TPS65011 internally sets/clears these registers:
The following describes the function of the 0x03 (MASK1), 0x04 (MASK2) and 0x0F (MASK3) registers:
GPIO interrupts are located by reading the 0x10 (DEFGPIO) register. The application CPU stores, or can read from DEFGPIO<7:4>, which GPIO is set to input or output. This information together with the information on which edge the interrupt was generated (the CPU either knows this or can read it from MASK3<7:4>) determines whether the CPU is looking for a 0 or a 1 in DEFGPIO<3:0>. A GPIO interrupt is blocked from the INT pin by setting the relevant MASK3<3:0> bit; this must be done by the CPU, there is no auto-acknowledge for the GPIO interrupts.
The serial interface is compatible with the standard and fast mode I2C specifications, allowing transfers at up to 400 kHz. The interface adds flexibility to the power supply solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements and charger status to be monitored. Register contents remain intact as long as VCC remains above 2 V. The TPS65011 has a 7-bit address with the LSB set by the IFLSB pin, this allows the connection of two devices with the same address to the same bus. The 6 MSBs are 100100. Attempting to read data from register addresses not listed in this section results in FFh being read out.
For normal data transfer, DATA is allowed to change only when CLK is low. Changes when CLK is high are reserved for indicating the start and stop conditions. During data transfer, the data line must remain stable whenever the clock line is high. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. When addressed, the TPS65011 device generates an acknowledge bit after the reception of each byte. The master device (microprocessor) must generate an extra clock pulse that is associated with the acknowledge bit. The TPS65011 device must pull down the DATA line during the acknowledge clock pulse so that the DATA line is a stable low during the high period of the acknowledge clock pulse. The DATA line is a stable low during the high period of the acknowledge-related clock pulse. Setup and hold times must be taken into account. During read operations, a master must signal the end of data to the slave by not generating an acknowledge bit on the last byte that was clocked out of the slave. In this case, the slave TPS65011 device must leave the data line high to enable the master to generate the stop condition.
The I2C interface accepts data as soon as the voltage at VCC is higher than the undervoltage lockout threshold and one power rail of the converter (main, core, or one of the LDOs) is operating. Therefore, the I2C interface is not operating after applying the battery voltage as the device automatically enters the WAIT mode with all rails off.
When the device is in WAIT mode, the I2C registers are reset to their default values if all voltage rails are off. If the device is in WAIT mode and one power rail is left on, the I2C interface is operating and the registers are not reset after leaving the WAIT mode.
CHGSTATUS | B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 |
---|---|---|---|---|---|---|---|---|
Name | USB charge | AC charge | Thermal Suspend |
Term Current | Taper Timeout | Chg Timeout | Prechg Timeout | BattTemp error |
Default | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Read/write | R | R | R | R | R/W | R/W | R/W | R |
The CHGSTATUS register contents indicate the status of charge.
Bit 7 - USB charge:
Bit 6 - AC charge:
Bit 5 - Thermal suspend:
Bit 4 - Term current:
Bit 3 - 1 Prechg Timeout, Chg Timeout, Taper Timeout:
Bit 0 - BattTemp error: Battery temperature error
B1-4 may be reset via the serial interface in order to force a reset of the charger. Any attempt to write to B0 and B5-7 is ignored. A 1 in B<7:0> sets the INT pin active unless the corresponding bit in the MASK register is set.
REGSTATUS | B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 |
---|---|---|---|---|---|---|---|---|
Bit name | PB_ONOFF | BATT_COVER | UVLO | PGOOD LDO2 | PGOOD LDO1 | PGOOD MAIN | PGOOD CORE | |
Default | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Read/write | R | R | R | R | R | R | R | R |
Bit 7 - PB_ONOFF:
Bit 6 - BATT_COVER:
Bit 5 - UVLO:
Bit 4 - not implemented
Bit 3 - PGOOD LDO2:
Bit 2 - PGOOD LDO1:
Bit 1 - PGOOD MAIN:
Bit 0 - PGOOD CORE:
A rising edge in the REGSTATUS register contents causes INT to be driven low if it is not masked in the MASK2.
MASK1 | B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 |
---|---|---|---|---|---|---|---|---|
Bit name | Mask USB | Mask AC | Mask Thermal Suspend |
Mask Term | Mask Taper | Mask Chg | Mask Prechg | Mask BattTemp |
Default | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
Read/write | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
The MASK1 register is used to mask all or any of the conditions in the corresponding CHGSTATUS<7:0> positions being indicated at the INT pin. Default is to mask all.
MASK2 | B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 |
---|---|---|---|---|---|---|---|---|
Bit name | Mask PB_ONOFF | Mask BATT_COVER | Mask UVLO | Mask PGOOD LDO2 | Mask PGOOD LDO1 | Mask PGOOD MAIN | Mask PGOOD CORE | |
Default | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
Read/write | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
The MASK2 register is used to mask all or any of the conditions in the corresponding REGSTATUS<7:0> positions being indicated at the INT pin. Default is to mask all.
ACKINT1 | B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 |
---|---|---|---|---|---|---|---|---|
Bit name | Ack USB | Ack AC | Ack Thermal Shutdown | Ack Term | Ack Taper | Ack Chg | Ack Prechg | Ack BattTemp |
Default | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Read/write | R | R | R | R | R | R | R | R |
The ACKINT1 register is internally used to acknowledge any of the interrupts in the corresponding CHGSTATUS<7:0> positions. When this is done, the acknowledged interrupt is no longer fed through to the INT pin and so the INT pin becomes free to indicate the next pending interrupt. If none exists, then the INT pin goes high, else it will remain low. A 1 at any position in ACKINT1 is automatically cleared when the corresponding interrupt condition in CHGSTATUS is removed. The application processor should not normally need to access the ACKINT1 register.
ACKINT2 | B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 |
---|---|---|---|---|---|---|---|---|
Bit name & function | Ack PB_ONOFF | Ack BATT_ COVER |
Ack UVLO | Ack PGOOD LDO2 | Ack PGOOD LDO1 | Ack PGOOD MAIN | Ack PGOOD CORE | |
Default | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Read/write | R | R | R | R | R | R | R | R |
The ACKINT2 register is internally used to acknowledge any of the interrupts in the corresponding REGSTATUS<7:0> positions. When this is done, the acknowledged interrupt is no longer fed through to the INT pin and so the INT pin becomes free to indicate the next pending interrupt. If none exists, then the INT pin goes high, else it will remain low. A 1 at any position in ACKINT2 is automatically cleared when the corresponding interrupt condition in REGSTATUS is removed. The application processor should not normally need to access the ACKINT2 register.
CHGCONFIG | B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 |
---|---|---|---|---|---|---|---|---|
Bit name | AUA | Charger reset | Fast charge timer + taper timer enabled | MSB charge current | LSB charge current | USB / 100 mA 500 mA | USB charge allowed | Charge enable |
Default | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 |
Read/write | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
The CHGCONFIG register is used to configure the charger.
Bit 7 - AUA:
Bit 6 - Charger reset:
Bit 5 - Fast charge timer + taper timer enabled:
Bit 4, Bit 3 - MSB/LSB Charge current:
B4:B3 | CHARGE CURRENT RATE |
---|---|
11 | Maximum current set by the external resistor at the ISET pin |
10 | 75% of maximun |
01 | 50% of maximun |
00 | 25% of maximun |
Bit 2 - USB 100 mA / 500 mA:
Bit 1 - USB charge allowed:
Bit 0 - Charge enable:
LED1_ON | B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 |
---|---|---|---|---|---|---|---|---|
Bit name | PG1 | LED1 ON6 | LED1 ON5 | LED1 ON4 | LED1 ON3 | LED1 ON2 | LED1 ON1 | LED1 ON 0 |
Default | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Read/write | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
The LED1_ON and LED1_PER registers can be used to take control of the PG open drain output normally controlled by the charger.
Bit 7 - PG1: Control of the PG pin is determined by PG1 and PG2 according to the table under LED1_PER register
Bit 6 - BIT 0 - LED1_ON<6:0> are used to program the on-time of the open drain output transistor at the PG pin. The minimum on-time is typically 10 ms and one LSB corresponds to a 10-ms step change in the on-time.
LED1_PER | B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 |
---|---|---|---|---|---|---|---|---|
Bit name | PG2 | LED1 PER6 | LED1 PER5 | LED1 PER4 | LED1 PER3 | LED1 PER2 | LED1 PER1 | LED1 PER 0 |
Default | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Read/write | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
Bit 7 - PG2: Control of the PG pin is determined by PG1 and PG2 according to the following table. Default shown in bold.
PG1 | PG2 | BEHAVIOR OF PG OPEN DRAIN OUTPUT |
---|---|---|
0 | 0 | Under charger control |
0 | 1 | Blink |
1 | 0 | Off |
1 | 1 | Always On |
Bit 6-Bit 0 - LED1_PER<6:0> are used to program the time period of the open-drain output transistor at the PG pin. The minimum period is typically 100 ms and one LSB corresponds to a 100-ms step change in the period.
LED2_ON | B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 |
---|---|---|---|---|---|---|---|---|
Bit name | LED21 | LED2 ON6 | LED2 ON5 | LED2 ON4 | LED2 ON3 | LED2 ON2 | LED2 ON1 | LED2 ON0 |
Default | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Read/write | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
The LED2_ON and LED2_PER registers are used to control the LED2 open-drain output.
Bit 7 LED22: Control is determined by LED21 and LED22 according to the table under LED2_PER register.
Bit 6-Bit 0 - LED2_ON<6:0> are used to program the on-time of the open drain output transistor at the LED2 pin. The minimum on-time is typically 10 ms and one LSB corresponds to a 10-ms step change in the on-time.
LED2_PER | B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 |
---|---|---|---|---|---|---|---|---|
Bit name | LED22 | LED2 PER6 | LED2 PER5 | LED2 PER4 | LED2 PER3 | LED2 PER2 | LED2 PER1 | LED2 PER 0 |
Default | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Read/write | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
Bit 7 LED22: Control is determined by LED21 and LED22 according to the table. Default shown in bold.
Bit 6-Bit 0 - LED2_ON<6:0> are used to program the on-time of the open drain output transistor at the LED2 pin. The minimum on-time is typically 100 ms and one LSB corresponds to a 100-ms step change in the on-time.
LED21 | LED22 | BEHAVIOR OF LED2 OPEN DRAIN OUTPUT |
---|---|---|
0 | 0 | Off |
0 | 1 | Blink |
1 | 0 | Off |
1 | 1 | Always On |
VDCDC1 | B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 |
---|---|---|---|---|---|---|---|---|
Bit name | FPWM | UVLO1 | UVLO0 | ENABLE SUPPLY | ENABLE LP | MAIN DISCHARGE | MAIN1 | MAIN0 |
Default | 0 | 0 | 1 | 1 | 0 | 0 | 1 | DEFMAIN |
Read/write | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
The VDCDC1 register is used to program the VMAIN switching converter.
Bit 7 - FPWM: forced PWM mode for DC-DC converters.
Bit 6-Bit 5 - UVLO<1:0>: The undervoltage threshold voltage is set by UVLO1 and UVLO0 according to the below table, with the reset in bold.
UVLO1 | UVLO0 | VUVLO |
---|---|---|
0 | 0 | 2.5 V |
0 | 1 | 2.75 V |
1 | 0 | 3.0 V |
1 | 1 | 3.25 V |
Bit 4 - ENABLE SUPPLY (selects between LOW-POWER mode and WAIT mode):
Bit 3 - ENABLE LP:
Bit 2 - MAIN DISCHARGE:
Bit 1-Bit 0 - MAIN<1:0>: The VMAIN converter output voltages are set according to the following table, with the reset in bold set by the DEFMAIN pin. The default voltage can subsequently be over-written via the serial interface after start-up.
MAIN1 | MAIN0 | VMAIN |
---|---|---|
0 | 0 | 2.5 V |
0 | 1 | 2.75 V |
1 | 0 | 3.0 V |
1 | 1 | 3.3 V |
VDCDC2 | B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 |
---|---|---|---|---|---|---|---|---|
Bit name | LP_COREOFF | CORE2 | CORE1 | CORE0 | CORELP1 | CORELP0 | VIB | CORE DISCHARGE |
Default | 0 | 1 | 1 | DEFCORE | 1 | 0 | 0 | 0 |
Read/write | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
The VDCDC2 register is used to program the VCORE switching converter output voltage. It is programmable in 8 steps between 0.85 V and 1.8 V. The reset is governed by the DEFCORE pin; DEFCORE=0 sets an output voltage of 1.5 V. DEFCORE=1 sets an output voltage of 1.8 V.
Bit 7 - LP_COREOFF:
Bit 6-Bit 4 - CORE<2:0>: The following table shows all possible values of VCORE. The reset can subsequently be overwritten via the serial interface after start-up.
CORE2 | CORE1 | CORE0 | VCORE |
---|---|---|---|
0 | 0 | 0 | 0.85 V |
0 | 0 | 1 | 1.0 V |
0 | 1 | 0 | 1.1 V |
0 | 1 | 1 | 1.2 V |
1 | 0 | 0 | 1.3 V |
1 | 0 | 1 | 1.4 V |
1 | 1 | 0 | 1.5 V |
1 | 1 | 1 | 1.8 V |
Bit 3-Bit 2 - CORELP<1:0>: CORELP1 and CORELP0 can be used to set the VCORE voltage in low power mode. In low power mode, CORE2 is effectively 0, and CORE1, CORE0 take on the values programmed at CORELP1 and CORELP0, default 10 giving VCORE = 1.1 V as default in low power mode. When low power mode is exited, VCORE reverts to the value set by CORE2, CORE1, and CORE0.
Bit 1 - VIB:
Bit 0 - CORE DISCHARGE:
VREGS1 | B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 |
---|---|---|---|---|---|---|---|---|
Bit name | LDO2 enable | LDO2 OFF / nSLP | LDO21 | LDO20 | LDO1 enable | LDO1 OFF / nSLP | LDO11 | LDO10 |
Default | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
Read/write | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
The VREGS1 register is used to program and enable LDO1 and LDO2 and to set their behavior when low-power mode is active. The LDO output voltages can be set either on the fly, while the relevant LDO is disabled, or simultaneously when the relevant enable bit is set. Note that both LDOs are per default ON.
Bit 7-Bit 6 - The function of the LDO2 enable and LDO2 OFF/nSLP bits is shown in the following table. See the Power-Up Sequencing section for details of low-power mode.
LDO2 ENABLE | LDO2 OFF / nSLP | LDO STATUS IN NORMAL MODE | LDO STATUS IN LOW-POWER MODE |
---|---|---|---|
0 | X | OFF | OFF |
1 | 0 | ON, full power | ON, reduced power / performance |
1 | 1 | ON, full power | OFF |
Bit 5-Bit 4 - LDO2<1:0>: LDO2 has a default output voltage of 1.8 V. If so desired, this can be changed at the same time as it is enabled via the serial interface.
LDO21 | LDO20 | VLDO2 |
---|---|---|
0 | 0 | 1.8 V |
0 | 1 | 2.5 V |
1 | 0 | 3.0 V |
1 | 1 | 3.3 V |
Bit 3-Bit 2 - The function of the LDO1 enable and LDO1 OFF / nSLP bits is shown in the following table. See the Power-Up Sequencing section for details of low-power mode. Note that programming LDO1 to a higher voltage may force a system power-on reset if the increase is in the 10% or greater range.
LDO1 ENABLE | LDO1 OFF / nSLP | LDO STATUS IN NORMAL MODE | LDO STATUS IN LOW-POWER MODE |
---|---|---|---|
0 | X | OFF | OFF |
1 | 0 | ON, full power | ON, reduced power and performance |
1 | 1 | ON, full power | OFF |
Bit 1-Bit 0 - LDO1<1:0>: The LDO1 output voltage is per default set externally. If so desired, this can be changed via the serial interface.
LDO11 | LDO10 | VLDO1 |
---|---|---|
0 | 0 | ADJ |
0 | 1 | 2.5 V |
1 | 0 | 2.75 V |
1 | 1 | 3.0 V |
MASK3 | B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 |
---|---|---|---|---|---|---|---|---|
Bit name | Edge trigger GPIO4 | Edge trigger GPIO3 | Edge trigger GPIO2 | Edge trigger GPIO1 | Mask GPIO4 | Mask GPIO3 | Mask GPIO2 | Mask GPIO1 |
Default | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Read/write | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
The MASK3 register must be considered when any of the GPIO pins are programmed as inputs.
Bit 7-Bit 4 - Edge trigger GPIO<4:1>: determine whether the respective GPIO generates an interrupt at a rising or a falling edge.
Bit 3-Bit 0 - Mask GPIO<4:1>: can be used to mask the corresponding interrupt. Default is unmasked (mask GPIOx = 0).
DEFGPIO | B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 |
---|---|---|---|---|---|---|---|---|
Bit name | IO4 | IO3 | IO2 | IO1 | Value GPIO4 | Value GPIO3 | Value GPIO2 | Value GPIO1 |
Default | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Read/write | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
The DEFGPIO register is used to define the GPIO pins to be either input or output.
Bit 7-Bit 4 - IO<4:1>:
Bit 3-Bit 0 - Value GPIO<4:1>: If a GPIO is programmed to be an output, then the signal output is determined by the corresponding bit. The output circuit for each GPIO is an open drain NMOS requiring an external pullup resistor.
If a particular GPIO is programmed to be an input, then the contents of the relevant bit in B3-0 is defined by the logic level at the GPIO pin. A logic low forces a 0 and a logic high forces a 1. If a GPIO is programmed to be an input, then any attempt to write to the relevant bit in B3-0 is ignored.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The VCORE and VMAIN converter are always enabled in a typical application. The VCORE output voltage can be disabled or reduced from 1.5 V to a lower, preset voltage under processor control. When the processor enters the sleep mode, a high signal on the LOW_PWR pin initiates the change.
VCORE typically supplies the digital part of the audio codec. When the processor is in sleep or low-power mode, the audio codec is powered off, so the VCORE voltage can be programmed to lower voltages without a problem. A typical audio codec (e.g., TI AIC23) consumes about 20-mA to 30-mA current from the VCORE power supply.
Supply LDO1 from VMAIN as shown in Figure 43. If this is not done, then subsequent to a UVLO, OVERTEMP, or BATT_COVER = 0 condition, the RESPWRON signal goes high before the VCORE rail has ramped and stabilized. Therefore, the processor core does not receive a power-on-reset signal.
Each DC-DC converter requires an external inductor and filter capacitor, capable of sustain the intended current with an acceptable voltage ripple. LDOs must have external filter capacitors, and LDO1 requires an external feedback network for regulation. Every input supply rail requires a decoupling capacitor close to the pin, and to avoid unintended states, logic inputs without internal resistors must not be left floating.
The main and the core converters in the TPS65011 typically use a 6.2-µH and a 10-µH output inductor, respectively. Larger or smaller inductor values can be used to optimize the performance of the device for specific operation conditions. The selected inductor has to be rated for its dc resistance and saturation current. The dc resistance of the inductance influences directly the efficiency of the converter. Therefore, an inductor with lowest dc resistance is selected for highest efficiency.
Equation 3 calculates the maximum inductor current under static load conditions. The saturation current of the inductor must be rated higher than the maximum inductor current as calculated with Equation 3. This is needed because during heavy load transient, the inductor current rises above the value calculated under Equation 3.
where
The highest inductor current occurs at maximum VI.
Open core inductors have a soft saturation characteristic, and they can usually handle higher inductor currents versus a comparable shielded inductor.
A more conservative approach is to select the inductor current rating just for the maximum switch current of the TPS65011 (2 A for the main converter and 0.8 A for the core converter). Keep in mind that the core material from inductor to inductor differs and has an impact on the efficiency especially at high switching frequencies.
Refer to Table 5 and the typical applications for possible inductors
DEVICE | INDUCTOR VALUE | DIMENSIONS | COMPONENT SUPPLIER |
---|---|---|---|
Core converter | 10 µH | 6,0 mm × 6,0 mm × 2,0 mm | Sumida CDRH5D18-100 |
10 µH | 5,0 mm × 5,0 mm × 3,0 mm | Sumida CDRH4D28-100 | |
Main converter | 4.7 µH | 5,5 mm × 6,6 mm x 1,0 mm | Coilcraft LPO1704-472M |
4.7 µH | 5,0 mm × 5,0 mm × 3,0 mm | Sumida CDRH4D28C-4.7 | |
4.7 µH | 5,2 mm × 5,2 mm × 2,5 mm | Coiltronics SD25-4R7 | |
5.3 µH | 5,7 mm × 5,7 mm × 3,0 mm | Sumida CDRH5D28-5R3 | |
6.2 µH | 5,7 mm × 5,7 mm × 3,0 mm | Sumida CDRH5D28-6R2 | |
6.0 µH | 7,0 mm × 7,0 mm × 3,0 mm | Sumida CDRH6D28-6R0 |
The advanced fast response voltage mode control scheme of the inductive converters implemented in the TPS65011 allow the use of small ceramic capacitors with a typical value of 22 µF for the main converter and 10 µF for the core converter without having large output voltage under and overshoots during heavy load transients. Ceramic capacitors having low ESR values have the lowest output voltage ripple and are recommended. If required tantalum capacitors with an ESR < 100 ΩR may be used as well.
Refer to Table 6 for recommended components.
If ceramic output capacitors are used, the capacitor RMS ripple current rating always meet the application requirements. Just for completeness the RMS ripple current is calculated as:
At nominal load current, the inductive converters operate in PWM mode and the overall output voltage ripple is the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and discharging the output capacitor:
Where the highest output voltage ripple occurs at the highest input voltage VI.
At light load currents, the converters operate in power save mode and the output voltage ripple is independent of the output capacitor value. The output voltage ripple is set by the internal comparator thresholds. The typical output voltage ripple is 1% of the nominal output voltage. If the output voltage for the core converter is programmed to its lowest voltage of 0.85 V, the output capacitor must be increased to 22 µF for low output voltage ripple. This is because the current in the inductor decreases slowly during the off-time and further increases the output voltage even when the PMOS is off. This effect increases with low output voltages.
A pulsating input current is the nature of the buck converter. Therefore, a low ESR input capacitor is required for best input voltage filtering. It also minimizes the interference with other circuits caused by high input voltage spikes. The main converter needs a 22-µF ceramic input capacitor and the core converter a 10-µF ceramic capacitor. The input capacitor for the main and the core converter can be combined and one 22-µF capacitor can be used instead, because the two converters operate with a phase shift of 270 degrees. The input capacitor can be increased without any limit for better input voltage filtering. The VCC pin must be separated from the input for the main and the core converter. A filter resistor of up to 100 Ω and a 1-µF capacitor is used for decoupling the VCC pin from switching noise.
CAPACITOR VALUE | CASE SIZE | COMPONENT SUPPLIER | COMMENTS |
---|---|---|---|
22 µF | 1206 | TDK C3216X5R0J226M | Ceramic |
22 µF | 1206 | Taiyo Yuden JMK316BJ226ML | Ceramic |
22 µF | 1210 | Taiyo Yuden JMK325BJ226MM | Ceramic |
The output voltage of LDO1 is set with a resistor divider at the feedback pin. The sum of the two resistors must not exceed 1 MΩ to minimize voltage changes due to leakage current into the feedback pin. The output voltage for LDO1 after start up is the voltage set by the external resistor divider. It can be reprogrammed with the I2C interface to the three other values defined in the register VREGS1.
The input capacitors for the DC-DC converters should be placed as close as possible to the VINMAIN, VINCORE, and VCC pins.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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