SLVS551A December   2004  – September 2015 TPS65014

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Electrical Characteristics: Battery Charger
    7. 6.7  Dissipation Ratings
    8. 6.8  Serial Interface Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Step-Down Converters, VMAIN and VCORE
        1. 7.3.1.1 Forced PWM
        2. 7.3.1.2 Dynamic Voltage Positioning
        3. 7.3.1.3 Soft-Start
        4. 7.3.1.4 100% Duty Cycle Low Dropout Operation
        5. 7.3.1.5 Active Discharge When Disabled
        6. 7.3.1.6 Power-Good Monitoring
        7. 7.3.1.7 Overtemperature Shutdown
      2. 7.3.2 Low-Dropout Voltage Regulators
        1. 7.3.2.1 Power-Good Monitoring
        2. 7.3.2.2 Enabling and Sequencing
      3. 7.3.3 Undervoltage Lockout
      4. 7.3.4 Power-Up Sequencing
        1. 7.3.4.1 TPS65014 Power State Descriptions
          1. 7.3.4.1.1 State 1: No Power
          2. 7.3.4.1.2 State 2: ON
          3. 7.3.4.1.3 State 3: Low-Power Mode
          4. 7.3.4.1.4 State 4: Shutdown
      5. 7.3.5 System Reset and Control Signals
      6. 7.3.6 Vibrator Driver
      7. 7.3.7 LED2 Output
      8. 7.3.8 Interrupt Management
      9. 7.3.9 Serial Interface
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Save Mode Operation
      2. 7.4.2 Sleep Mode
    5. 7.5 Register Maps
      1. 7.5.1  CHGSTATUS Register (offset = 01h) (reset: 00h)
      2. 7.5.2  REGSTATUS Register (offset = 02h) (reset: 00h)
      3. 7.5.3  MASK1 Register (offset = 03h) (reset: FFh)
      4. 7.5.4  MASK2 Register (offset = 04h) (reset: FFh)
      5. 7.5.5  ACKINT1 Register (offset = 05h) (reset: 00h)
      6. 7.5.6  ACKINT2 Register (offset: 06h) (reset: 00h)
      7. 7.5.7  CHGCONFIG Register (offset: 07h) (reset: 1Bh)
      8. 7.5.8  LED1_ON Register (offset: 08h) (reset: 00h)
      9. 7.5.9  LED1_PER Register (offset: 09h) (reset: 00h)
      10. 7.5.10 LED2_ON Register (offset: 0Ah) (reset: 00h)
      11. 7.5.11 LED2_PER (offset: 0Bh) (reset: 00h)
      12. 7.5.12 VDCDC1 Register (offset: 0Ch) (reset: 32h/33h)
      13. 7.5.13 VDCDC2 Register (offset: 0Dh) (reset: 60h/70h)
      14. 7.5.14 VREGS1 Register (offset: 0Eh) (reset: 88h)
      15. 7.5.15 MASK3 Register (offset: 0Fh) (reset: 00h)
      16. 7.5.16 DEFGPIO Register (offset = 10h) (reset: 00h)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Inductor Selection for the Main and the Core Converter
        2. 8.2.2.2 Output Capacitor Selection
        3. 8.2.2.3 Input Capacitor Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Battery Charger
      1. 9.1.1 Autonomous Power Source Selection
      2. 9.1.2 Temperature Qualification
      3. 9.1.3 Battery Preconditioning
      4. 9.1.4 Battery Charge Current
      5. 9.1.5 Battery Voltage Regulation
      6. 9.1.6 Charge Termination and Recharge
      7. 9.1.7 PG Output
      8. 9.1.8 Thermal Considerations for Setting Charge Current
    2. 9.2 LDO1 Output Voltage Adjustment
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS65014 is an integrated power- and battery-management IC designed to pair with various application processors powered by one Li-ion or Li-polymer cell and which require multiple rails.

8.2 Typical Application

The VCORE and VMAIN converter are always enabled in a typical application. The VCORE output voltage can be disabled or reduced from 1.5 V to a lower, preset voltage under processor control. When the processor enters the sleep mode, a high signal on the LOW_PWR pin initiates the change.

VCORE typically supplies the digital part of the audio codec. When the processor is in sleep or low-power mode, the audio codec is powered off, so the VCORE voltage can be programmed to lower voltages without a problem. A typical audio codec (such as the TI AIC23) consumes about 20-mA to 30-mA current from the VCORE power supply.

Supply LDO1 from VMAIN as shown in Figure 54. If this is not done, then subsequent to a UVLO, OVERTEMP, or BATT_COVER = 0 condition, the RESPWRON signal goes high before the VCORE rail has ramped and stabilized. Therefore, the processor core does not receive a power-on-reset signal.

TPS65014 ai_typ_cir_lvs551.gif Figure 54. Typical Application Circuit
TPS65014 ai_LP_typcir_lvs551.gif Figure 55. Typical Application Circuit in Low-Power Mode

8.2.1 Design Requirements

Each DC-DC converter requires an external inductor and filter capacitor, capable of sustaining the intended current with an acceptable voltage ripple. LDOs must have external filter capacitors, and LDO1 requires an external feedback network for regulation. Every input supply rail requires a decoupling capacitor close to the pin. To avoid unintended states, logic inputs without internal resistors must not be left floating.

8.2.2 Detailed Design Procedure

8.2.2.1 Inductor Selection for the Main and the Core Converter

The main and the core converters in the TPS65014 typically use a 6.2-µH and a 10-µH output inductor, respectively. Larger or smaller inductor values can be used to optimize the performance of the device for specific operation conditions. The selected inductor must be rated for its DC resistance and saturation current. The DC resistance of the inductance influences directly the efficiency of the converter. Therefore, an inductor with lowest DC resistance is selected for highest efficiency.

Equation 3 calculates the maximum inductor current under static load conditions. The saturation current of the inductor must be rated higher than the maximum inductor current as calculated with Equation 3. This is necessary because during heavy load transient, the inductor current rises above the value calculated in Equation 4.

Equation 3. TPS65014 Q_delta_IL_lvs551.gif
Equation 4. TPS65014 Q_IL_max_lvs551.gif

where

  • f = Switching frequency (1.25-MHz typical)
  • L = Inductor value
  • ΔIL= Peak-to-peak inductor ripple current
  • ILmax = Maximum inductor current

The highest inductor current occurs at maximum VI.

Open core inductors have a soft saturation characteristic, and they can usually handle higher inductor currents versus a comparable shielded inductor.

A more conservative approach is to select the inductor current rating just for the maximum switch current of the TPS65014 (2 A for the main converter and 0.8 A for the core converter). The core material from inductor to inductor differs and has an impact on the efficiency, especially at high switching frequencies.

See Table 31 and the typical applications for possible inductors

Table 31. Tested Inductors

DEVICE INDUCTOR VALUE DIMENSIONS COMPONENT SUPPLIER
Core converter 10 µH 6 mm × 6 mm × 2 mm Sumida CDRH5D18-100
10 µH 5 mm × 5 mm × 3 mm Sumida CDRH4D28-100
Main converter 4.7 µH 5.5 mm × 6.6 mm x 1 mm Coilcraft LPO1704-472M
4.7 µH 5 mm × 5 mm × 3 mm Sumida CDRH4D28C-4.7
4.7 µH 5.2 mm × 5.2 mm × 2.5 mm Coiltronics SD25-4R7
5.3 µH 5.7 mm × 5.7 mm × 3 mm Sumida CDRH5D28-5R3
6.2 µH 5.7 mm × 5.7 mm × 3 mm Sumida CDRH5D28-6R2
6 µH 7 mm × 7 mm × 3 mm Sumida CDRH6D28-6R0

8.2.2.2 Output Capacitor Selection

The advanced fast response voltage-mode control scheme of the inductive converters implemented in the TPS65014 allows the use of small ceramic capacitors with a typical value of 22 µF for the main converter and
10 µF for the core converter, without having large output voltage undershoots and overshoots during heavy load transients. TI recommends ceramic capacitors with low ESR values and the lowest output voltage ripple. If required, tantalum capacitors with an ESR < 100 Ω may be used as well.

See Table 32 for recommended components.

If ceramic output capacitors are used, the capacitor RMS ripple current rating always meet the application requirements. For completeness, the RMS ripple current is calculated as in Equation 5:

Equation 5. TPS65014 Q_Irms_lvs551.gif

At nominal load current, the inductive converters operate in PWM mode, and the overall output voltage ripple is the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and discharging the output capacitor, as in Equation 6:

Equation 6. TPS65014 Q_delta_VO_lvs551.gif

Where the highest output voltage ripple occurs at the highest input voltage VI.

At light load currents, the converters operate in power save mode and the output voltage ripple is independent of the output capacitor value. The output voltage ripple is set by the internal comparator thresholds. The typical output voltage ripple is 1% of the nominal output voltage. If the output voltage for the core converter is programmed to its lowest voltage of 0.85 V, the output capacitor must be increased to 22 µF for low output voltage ripple. This is because the current in the inductor decreases slowly during the off-time and further increases the output voltage, even when the PMOS is off. This effect increases with low output voltages.

8.2.2.3 Input Capacitor Selection

A pulsating input current is the nature of the buck converter. Therefore, a low ESR input capacitor is required for best input voltage filtering. It also minimizes the interference with other circuits caused by high input voltage spikes. The main converter requires a 22-µF ceramic input capacitor, and the core converter requires a 10-µF ceramic capacitor. The input capacitor for the main and the core converter can be combined and one 22-µF capacitor can be used instead, because the two converters operate with a phase shift of 270 degrees. The input capacitor can be increased without any limit for better input voltage filtering. The VCC pin should be separated from the input for the main and the core converter. A filter resistor of up to 100 Ω and a 1-µF capacitor is used for decoupling the VCC pin from switching noise.

Table 32. Possible Capacitors

CAPACITOR VALUE CASE SIZE COMPONENT SUPPLIER COMMENTS
22 µF 1206 TDK C3216X5R0J226M Ceramic
22 µF 1206 Taiyo Yuden JMK316BJ226ML Ceramic
22 µF 1210 Taiyo Yuden JMK325BJ226MM Ceramic

8.2.3 Application Curves

TPS65014 eff0_core_lvs551.gif Figure 56. Efficiency vs Output Current
TPS65014 eff0_main_lvs551.gif Figure 57. Efficiency vs Output Current