SLVS551A December   2004  – September 2015 TPS65014

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Electrical Characteristics: Battery Charger
    7. 6.7  Dissipation Ratings
    8. 6.8  Serial Interface Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Step-Down Converters, VMAIN and VCORE
        1. 7.3.1.1 Forced PWM
        2. 7.3.1.2 Dynamic Voltage Positioning
        3. 7.3.1.3 Soft-Start
        4. 7.3.1.4 100% Duty Cycle Low Dropout Operation
        5. 7.3.1.5 Active Discharge When Disabled
        6. 7.3.1.6 Power-Good Monitoring
        7. 7.3.1.7 Overtemperature Shutdown
      2. 7.3.2 Low-Dropout Voltage Regulators
        1. 7.3.2.1 Power-Good Monitoring
        2. 7.3.2.2 Enabling and Sequencing
      3. 7.3.3 Undervoltage Lockout
      4. 7.3.4 Power-Up Sequencing
        1. 7.3.4.1 TPS65014 Power State Descriptions
          1. 7.3.4.1.1 State 1: No Power
          2. 7.3.4.1.2 State 2: ON
          3. 7.3.4.1.3 State 3: Low-Power Mode
          4. 7.3.4.1.4 State 4: Shutdown
      5. 7.3.5 System Reset and Control Signals
      6. 7.3.6 Vibrator Driver
      7. 7.3.7 LED2 Output
      8. 7.3.8 Interrupt Management
      9. 7.3.9 Serial Interface
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Save Mode Operation
      2. 7.4.2 Sleep Mode
    5. 7.5 Register Maps
      1. 7.5.1  CHGSTATUS Register (offset = 01h) (reset: 00h)
      2. 7.5.2  REGSTATUS Register (offset = 02h) (reset: 00h)
      3. 7.5.3  MASK1 Register (offset = 03h) (reset: FFh)
      4. 7.5.4  MASK2 Register (offset = 04h) (reset: FFh)
      5. 7.5.5  ACKINT1 Register (offset = 05h) (reset: 00h)
      6. 7.5.6  ACKINT2 Register (offset: 06h) (reset: 00h)
      7. 7.5.7  CHGCONFIG Register (offset: 07h) (reset: 1Bh)
      8. 7.5.8  LED1_ON Register (offset: 08h) (reset: 00h)
      9. 7.5.9  LED1_PER Register (offset: 09h) (reset: 00h)
      10. 7.5.10 LED2_ON Register (offset: 0Ah) (reset: 00h)
      11. 7.5.11 LED2_PER (offset: 0Bh) (reset: 00h)
      12. 7.5.12 VDCDC1 Register (offset: 0Ch) (reset: 32h/33h)
      13. 7.5.13 VDCDC2 Register (offset: 0Dh) (reset: 60h/70h)
      14. 7.5.14 VREGS1 Register (offset: 0Eh) (reset: 88h)
      15. 7.5.15 MASK3 Register (offset: 0Fh) (reset: 00h)
      16. 7.5.16 DEFGPIO Register (offset = 10h) (reset: 00h)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Inductor Selection for the Main and the Core Converter
        2. 8.2.2.2 Output Capacitor Selection
        3. 8.2.2.3 Input Capacitor Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Battery Charger
      1. 9.1.1 Autonomous Power Source Selection
      2. 9.1.2 Temperature Qualification
      3. 9.1.3 Battery Preconditioning
      4. 9.1.4 Battery Charge Current
      5. 9.1.5 Battery Voltage Regulation
      6. 9.1.6 Charge Termination and Recharge
      7. 9.1.7 PG Output
      8. 9.1.8 Thermal Considerations for Setting Charge Current
    2. 9.2 LDO1 Output Voltage Adjustment
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

RGZ Package
48-Pin VQFN
Top View
TPS65014 po_lvs551.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
CHARGER SECTION
AC 40 I Charger input voltage from AC adapter. The AC pin can be left open or can be connected to ground if the charger is not used.
AGND2 44 — Analog ground connection. All analog ground pins are connected internally on the chip.
ISET 37 I External charge current setting resistor connection for use with AC adapter
PG 11 O Indicates when a valid power supply is present for the charger (open-drain)
TS 38 I Battery temperature sense input
USB 43 I Charger input voltage from USB port. The USB pin can be left open or can be connected to ground if the charger is not used.
VBAT_A 41 I Sense input for the battery voltage. Connect directly with the battery.
VBAT_B 42 O Power output of the battery charger. Connect directly with the battery.
Thermal Pad — — Connect the thermal pad to GND
SWITCHING REGULATOR SECTION
AGND3 45 — Analog ground connection. All analog ground pins are connected internally on the chip.
L1_A, L1_B 9, 10 — Switch pin of VMAIN converter. The VMAIN inductor is connected here.
L2 4 — Switch pin of VCORE converter. The VCORE inductor is connected here.
PGND1_A, PGND1_B 15, 16 — Power ground for VMAIN converter
PGND2 46 — Power ground for VCORE converter
SWITCHING REGULATOR SECTION (continued)
VCC 6 I Power supply for digital and analog circuitry of MAIN and CORE DC-DC converters. This must be connected to the same voltage supply as VINCORE and VINMAIN. Also supplies serial interface block
VCORE 48 I VCORE feedback voltage sense input, connect directly to VCORE
VMAIN 13 I VMAIN feedback voltage sense input, connect directly to VMAIN
VINMAIN_A, VINMAIN_B 7, 8 I Input voltage for VMAIN step-down converter. This must be connected to the same voltage supply as VINCORE and VCC.
VINCORE 5 I Input voltage for VCORE step-down converter. This must be connected to the same voltage supply as VINMAIN and VCC.
LDO REGULATOR SECTION
AGND1 21 — Analog ground connection. All analog ground pins are connected internally on the chip.
VFB_LDO1 23 I Feedback input from external resistive divider for LDO1
VINLDO1 22 I Input voltage for LDO1
VINLDO2 19 I Input voltage for LDO2
VLDO1 24 O Output voltage for LDO1
VLDO2 20 O Output and feedback voltage for LDO2
DRIVER SECTION
LED2 2 O LED driver, with blink rate programmable through the serial interface
VIB 3 O Vibrator driver, enabled through the serial interface
CONTROL AND I2C SECTION
BATT_COVER 39 I Indicates if battery cover is in place
DEFCORE 1 I Input signal indicating default VCORE voltage, 0 = 1.5 V, 1 = 1.8 V
DEFMAIN 12 I Input signal indicating default VMAIN voltage, 0 = 3 V, 1 = 3.3 V
GPIO1 26 I/O General-purpose open-drain input/output
GPIO2 25 I/O General-purpose open-drain input/output
GPIO3 18 I/O General-purpose open-drain input/output
GPIO4 17 I/O General-purpose open-drain input/output
HOT_RESET 31 I Push-button reset input used to reboot or wake up processor through the TPS65014
IFLSB 28 I LSB of serial interface address used to distinguish two devices with the same address
INT 35 O Indicates a charge fault or termination, or if any of the regulator outputs are below the lower tolerance level, active low (open-drain)
LOW_PWR 36 I Input signal indicating deep sleep mode, VCORE is lowered to predefined value or disabled
MPU_RESET 32 O Open-drain reset output generated by user activated HOT_RESET
PB_ONOFF 47 I Push-button enable pin, also used to wake up processor from low power mode
PS_SEQ 14 I Sets power-up/down sequence of step-down converters
PWRFAIL 34 O Open-drain output. Active low when UVLO comparator indicates low VBAT condition or when shutdown is about to occur due to an overtemperature condition or when the battery cover is removed (BATT_COVER has gone low).
RESPWRON 33 O Open-drain system reset output, generated according to the state of the VMAIN output voltage. If the main output is disabled, RESPWRON is active (in other words, low).
SCLK 30 I Serial interface clock line
SDAT 29 I/O Serial interface data/address
TPOR 27 I Sets the reset delay time at RESPWRON. TPOR = 0: Tn(RESPWRON) = 100 ms.
TPOR = 1: Tn(RESPWRON) = 1 s.