SLVS607D September   2005  – January 2016 TPS65020

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Electrical Characteristics: Supply Pins VCC, VINDCDC1, VINDCDC2, VINDCDC3
    7. 7.7  Electrical Characteristics: Supply Pins VBACKUP, VSYSIN, VRTC, VINLDO
    8. 7.8  Electrical Characteristics: VDCDC1 Step-Down Converter
    9. 7.9  Electrical Characteristics: VDCDC2 Step-Down Converter
    10. 7.10 Electrical Characteristics: VDCDC3 Step-Down Converter
    11. 7.11 Timing Requirements
    12. 7.12 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VRTC Output and Operation With or Without Backup Battery
      2. 8.3.2  Step-Down Converters, VDCDC1, VDCDC2, and VDCDC3
      3. 8.3.3  Power Save Mode Operation
      4. 8.3.4  Low Ripple Mode
      5. 8.3.5  Soft-Start
      6. 8.3.6  100% Duty Cycle Low-Dropout Operation
      7. 8.3.7  Active Discharge When Disabled
      8. 8.3.8  Power-Good Monitoring
      9. 8.3.9  Low-Dropout Voltage Regulators
      10. 8.3.10 Undervoltage Lockout
      11. 8.3.11 Power-Up Sequencing
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
      1. 8.5.1 System Reset + Control Signals
        1. 8.5.1.1 PB_IN and PB_OUT
        2. 8.5.1.2 Interrupt Management and the INT Pin
      2. 8.5.2 Serial Interface
    6. 8.6 Register Maps
      1. 8.6.1 VERSION Register Address: 00h (Read Only)
      2. 8.6.2 PGOODZ Register Address: 01h (Read Only)
      3. 8.6.3 MASK Register Address: 02h (Read and Write), Default Value: C0h
      4. 8.6.4 REG_CTRL Register Address: 03h (Read and Write), Default Value: FFh
      5. 8.6.5 CON_CTRL Register Address: 04h (Read and Write), Default Value: B0h
      6. 8.6.6 CON_CTRL2 Register Address: 05h (Read and Write), Default Value: 40h
      7. 8.6.7 DEFCORE. Register Address: 06h (Read and Write), Default Value: 14h/1Eh
      8. 8.6.8 DEFSLEW Register Address: 07h (Read and Write), Default Value: 06h
      9. 8.6.9 LDO_CTRL Register Address: 08h (Read and Write), Default Value: 23h
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Input Voltage Connection
      2. 9.1.2 Unused Regulators
      3. 9.1.3 Implementing a Push-Button On-Off Function Using PB_IN and PB_OUT
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection for the DC-DC Converters
        2. 9.2.2.2 Output Capacitor Selection
        3. 9.2.2.3 Input Capacitor Selection
        4. 9.2.2.4 Output Voltage Selection
        5. 9.2.2.5 VRTC Output
        6. 9.2.2.6 LDO1 and LDO2
        7. 9.2.2.7 TRESPWRON
        8. 9.2.2.8 VCC Filter
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Requirements for Supply Voltages Below 3.0 V
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers must validate and test their design implementation to confirm system functionality.

9.1 Application Information

9.1.1 Input Voltage Connection

The low power section of the control circuit for the step-down converters DCDC1, DCDC2, and DCDC3 is supplied by the VCC pin while the circuitry with high power such as the power stage is powered from the VINDCDC1, VINDCDC2, and VINDCDC3 pins. For proper operation of the step-down converters, VINDCDC1, VINDCDC2, VNDCDC3, and VCC must be tied to the same voltage rail. Step-down converters that are not planned to be used, still must be powered from their input pin on the same rails than the other step-down converters and VCC.

LDO1 and LDO2 share a supply voltage pin which can be powered from the VCC rails or from a voltage lower than VCC, for example, the output of one of the step-down converters as long as it is operated within the input voltage range of the LDOs. If both LDOs are not used, the VINLDO pin can be tied to GND.

9.1.2 Unused Regulators

In case a step-down converter is not used, its input supply voltage pin VINDCDCx still needs to be connected to the VCC rail along with supply input of the other step-down converters. TI recommends closing the control loop such that an inductor and output capacitor is added in the same way as it would be when operated normally. If one of the LDOs is not used, its output capacitor must be added as well. If both LDOs are not used, the input supply pin as well as the output pins of the LDOs (VINLDO, VLDO1, VLDO2) must be tied to GND.

9.1.3 Implementing a Push-Button On-Off Function Using PB_IN and PB_OUT

In mobile phone applications, the device must not automatically power up when the battery is inserted. Using PB_IN and PB_OUT prevents power up. After the main battery is inserted, the PB_OUT open-drain output is low. When this pins is connected with PWRFAIL, the signal is pulled low, preventing the Intel PXA270 start up.

See the latest version of Intels technical specifications about the Intel PXA270 Processor Family for additional information on the functionality of this chip and possible limitations.

TPS65020 push_butn_cir_lvs607.gif Figure 36. Control of the PXA270

9.2 Typical Application

TPS65020 typ_bulv_lvs607.gif Figure 37. Typical Configuration for the Intel PXA270 Bulverde Processor

9.2.1 Design Requirements

The TPS6502x devices have only a few design requirements. Use the following parameters for the design examples:

  • 1-μF bypass capacitor on VCC, located as close as possible to the VCC pin to ground
  • VCC and VINDCDCx must be connected to the same voltage supply with minimal voltage difference.
  • Input capacitors must be present on the VINDCDCx and VIN_LDO supplies if used
  • Output inductor and capacitors must be used on the outputs of the DCDC converters if used
  • Output capacitors must be used on the outputs of the LDOs if used

9.2.2 Detailed Design Procedure

9.2.2.1 Inductor Selection for the DC-DC Converters

Each of the converters in the TPS65020 typically use a 3.3-μH output inductor. Larger or smaller inductor values are used to optimize the performance of the device for specific operation conditions. The selected inductor has to be rated for its DC resistance and saturation current. The DC resistance of the inductance influences directly the efficiency of the converter. Therefore, an inductor with lowest DC resistance must be selected for highest efficiency.

For a fast transient response, a 2.2-μH inductor in combination with a 22-μF output capacitor is recommended.

Equation 8 calculates the maximum inductor current under static load conditions. The saturation current of the inductor must be rated higher than the maximum inductor current as calculated with Equation 8. This is needed because during heavy-load transient the inductor current rises above the value calculated under Equation 8.

Equation 8. TPS65020 q4_delta_lvs607.gif
Equation 9. TPS65020 q5_ilmax_lvs607.gif

where

  • f = Switching Frequency (1.5 MHz typical)
  • L = Inductor Value
  • ΔIL = Peak-to-Peak inductor ripple current
  • ILMAX = Maximum Inductor current

The highest inductor current occurs at maximum Vin.

Open-core inductors have a soft saturation characteristic, and they can usually handle higher inductor currents versus a comparable shielded inductor.

A more conservative approach is to select the inductor current rating just for the maximum switch current of the TPS65020 (2 A for the VDCDC1 and VDCDC2 converters, and 1.3 A for the VDCDC3 converter). The core material from inductor to inductor differs and has an impact on the efficiency especially at high switching frequencies.

See Table 16 and the typical applications for possible inductors.

Table 16. Tested Inductors

DEVICE INDUCTOR VALUE TYPE COMPONENT SUPPLIER
DCDC3 converter 3.3 μH CDRH2D14NP-3R3 Sumida
3.3 μH LPS3010-332 Coilcraft
3.3 μH VLF4012AT-3R3M1R3 TDK
2.2 μH VLF4012AT-2R2M1R5 TDK
2.2 μH NR3015T2R2 Taiyo-Yuden
DCDC2 converter 3.3 μH CDRH2D18/HPNP-3R3 Sumida
3.3 μH VLF4012AT-3R3M1R3 TDK
2.2 μH VLCF4020-2R2 TDK
DCDC1 converter 3.3 μH CDRH3D14/HPNP-3R2 Sumida
3.3 μH CDRH4D28C-3R2 Sumida
3.3 μH MSS5131-332 Coilcraft
2.2 μH VLCF4020-2R2 TDK

9.2.2.2 Output Capacitor Selection

The advanced fast response voltage mode control scheme of the inductive converters implemented in the TPS65020 allow the use of small ceramic capacitors with a typical value of 10 μF for a 3.3-μH inductor for each converter without having large output voltage under and overshoots during heavy-load transients.

For a fast transient response a 22-μF capacitor with a 2.2-μH inductor must be used on each converter.

Ceramic capacitors having low ESR values have the lowest output voltage ripple and are recommended. See Table 17 for recommended components.

If ceramic output capacitors are used, the capacitor RMS ripple current rating always meets the application requirements. Just for completeness, the RMS ripple current is calculated in Equation 10.

Equation 10. TPS65020 q6_irms_lvs607.gif

At nominal load current, the inductive converters operate in PWM mode. The overall output voltage ripple is the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and discharging the output capacitor:

Equation 11. TPS65020 q7_deltav_lvs607.gif

where

  • the highest output voltage ripple occurs at the highest input voltage Vin

At light-load currents, the converters operate in PSM and the output voltage ripple is dependent on the output capacitor value. The output voltage ripple is set by the internal comparator delay and the external capacitor. The typical output voltage ripple is less than 1% of the nominal output voltage.

9.2.2.3 Input Capacitor Selection

Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is required for best input voltage filtering and minimizing the interference with other circuits caused by high input voltage spikes. Each DC-DC converter requires a 10-μF ceramic input capacitor on its input pin VINDCDCx. The input capacitor is increased without any limit for better input voltage filtering. The VCC pin is separated from the input for the DC-DC converters. A filter resistor of up to 10R and a 1-μF capacitor is used for decoupling the VCC pin from switching noise. Note that the filter resistor may affect the UVLO threshold because up to 3 mA can flow through this resistor into the VCC pin when all converters are running in PWM mode.

Table 17. Possible Capacitors

CAPACITOR VALUE CASE SIZE COMPONENT SUPPLIER COMMENTS
22 μF 1206 TDK C3216X5R0J226M Ceramic
22 μF 1206 Taiyo Yuden JMK316BJ226ML Ceramic
10 μF 0805 Taiyo Yuden JMK212BJ106M Ceramic
10 μF 0805 TDK C2012X5R0J106M Ceramic
22 μF 0805 TDK C2012X5R0J226MT Ceramic
22 μF 0805 Taiyo Yuden JMK212BJ226MG Ceramic

9.2.2.4 Output Voltage Selection

The DEFDCDC1, DEFDCDC2, and DEFDCDC3 pins are used to set the output voltage for each step-down converter. See the table for the default voltages if the pins are pulled to GND or to VCC. If a different voltage is needed, an external resistor divider can be added to the DEFDCDCx pin as shown in Figure 38.

The output voltage of VDCDC3 is set with the I2C interface. If the voltage is changed from the default, using the DEFCORE register, the output voltage only depends on the register value. Any resistor divider at DEFDCDC3 does not change the voltage set with the register. Bit B6 in the CON_CTRL2 register is used to switch between the internal voltage setting or the voltage set with the external DEFDCDC3 pin for the VDCDC3 converter.

Table 18. Voltage Options

PIN LEVEL DEFAULT OUTPUT VOLTAGE
DEFDCDC1 VCC 3.3 V
GND 3 V
DEFDCDC2 VCC 2.5 V
GND 1.8 V
DEFDCDC3 VCC 1.55 V
GND 1.3 V

Figure 38 illustrations how to use an external resistor divider at DEFDCDCx.

TPS65020 resist_divider_lvs607.gif Figure 38. External Resistor Divider

When a resistor divider is connected to DEFDCDCx, the output voltage can be set from 0.6 V up to the input voltage V(bat). The total resistance (R1+R2) of the voltage divider must be kept in the 1-MR range to maintain a high efficiency at light load.

V(DEFDCDCx) = 0.6 V

Equation 12. TPS65020 q8_vout_lvs607.gif

9.2.2.5 VRTC Output

The VRTC output is typically connected to the VCC_Batt pin of a Intel PXA270 processor. During power-up of the processor, the TPS65020 internally switches from the LDO or the backup battery to the system voltage connected at the VSYSIN pin (see Figure 30). It is required to add a capacitor of 4.7-μF minimum to the VRTC pin, even the output may be unused.

9.2.2.6 LDO1 and LDO2

The LDOs default voltage is 1.1 V for LDO2 and 1.3 V for LDO1. They are intended to provide power to VCC_PLL and the VCC_SRAM pin on a PXA270 processor. The minimum output capacitor required is 2.2 μF. The LDOs output voltage is changed to different voltages between 1 V and 3.3 V using the I2C interface. Therefore, they can also be used as general-purpose LDOs in applications powering processors different from PXA270. The supply voltage for the LDOs needs to be connected to the VINLDO pin, giving the flexibility to connect the lowest voltage available in the system, and providing the highest efficiency.

9.2.2.7 TRESPWRON

This is the input to a capacitor that defines the reset delay time after the voltage at VRTC rises above 2.52 V. The timing is generated by charging and discharging the capacitor with a current of 2 μA between a threshold of 0.25 V and 1 V for 128 cycles. A 1-nF capacitor gives a delay time of 100 ms.

While there is no real upper and lower limit for the capacitor connected to TRESPWRON, TI recommends not leaving signal pins open.

Equation 13. TPS65020 q_t_reset_lvs607.gif

where

  • t(reset) is the reset delay time
  • C(reset) is the capacitor connected to the TRESPWRON pin

The minimum and maximum values for the timing parameters called ICONST (2 µA), TRESPWRON_UPTH
(1 V), and TRESPWRON_LOWTH (0.25 V) can be found under the Electrical Characteristics.

9.2.2.8 VCC Filter

An RC filter connected at the VCC input is used to prevent noise from the internal supply for the bandgap and other analog circuitry. A typical resistor value of 1 Ω and 1 μF is used to filter the switching spikes generated by the DC-DC converters. A resistor larger than 10 Ω must not be used because the current (up to 3 mA) into VCC causes a voltage drop at the resistor. This causes the undervoltage lockout circuitry connected internally at VCC to switch off too early.

9.2.3 Application Curves

Graphs were taken using the EVM with the inductor and output capacitor combinations in Table 19.

Table 19. Inductor and Output Capacitor Combinations

CONVERTER INDUCTOR OUTPUT CAPACITOR OUTPUT CAPACITOR VALUE
VDCDC1 VLCF4020-2R2 C2012X5R0J106M 2 × 10 μF
VDCDC2 VLCF4020-2R2 C2012X5R0J106M 2 × 10 μF
VDCDC3 VLF4012AT-2R2M1R5 C2012X5R0J106M 2 × 10 μF

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TPS65020 eff_33v1_io_lvs607.gif Figure 39. DCDC1 Efficiency
TPS65020 eff_155v1_io_lvs607.gif Figure 41. DCDC3 Efficiency
TPS65020 eff_18v1_io_lvs607.gif Figure 40. DCDC2 Efficiency