SLVS843B December   2008  – May 2018 TPS650250

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Detailed Block Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Dissipation Ratings
    6. 6.6  Electrical Characteristics
    7. 6.7  Electrical Characteristics VDCDC1
    8. 6.8  Electrical Characteristics VDCDC2
    9. 6.9  Electrical Characteristics VDCDC3
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Step-Down Converters, VDCDC1, VDCDC2 AND VDCDC3
      2. 7.3.2 Power Save Mode Operation
      3. 7.3.3 Soft Start
      4. 7.3.4 100% Duty Cycle Low Dropout Operation
      5. 7.3.5 Low Dropout Voltage Regulators
      6. 7.3.6 Undervoltage Lockout
      7. 7.3.7 PWRFAIL
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Typical Configuration For The Samsung Processor S3C6400-533MHz
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Inductor Selection for the DCDC Converters
        2. 8.2.3.2 Output Capacitor Selection
        3. 8.2.3.3 Input Capacitor Selection
        4. 8.2.3.4 Output Voltage Selection
        5. 8.2.3.5 Voltage Change on VDCDC3
        6. 8.2.3.6 Vdd_alive Output
        7. 8.2.3.7 LDO1 and LDO2
        8. 8.2.3.8 Vcc-Filter
      4. 8.2.4 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Electrical Characteristics

VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6V, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CONTROL SIGNALS: EN_DCDC1, EN_DCDC2, EN_DCDC3, EN_LDO, MODE, EN_VDD_ALIVE
VIH High level input voltage 1.45 VCC V
VIL Low level input voltage 0 0.4 V
IH Input bias current 0.01 0.1 μA
SUPPLY PINS: VCC, VINDCDC1, VINDCDC2, VINDCDC3
I(qPFM) Operating quiescent current PFM All 3 DCDC converters enabled, zero load and no switching, LDOs enabled VCC = 3.6V 135 170 μA
PFM All 3 DCDC converters enabled, zero load and no switching, LDO1, LDO2 = OFF, Vdd_alive = ON 75 100
PFM DCDC1 and DCDC2 converters enabled, zero load and no switching, LDO1, LDO2 = OFF, Vdd_alive = ON 55 80
PFM DCDC1 converter enabled, zero load and no switching, LDO1, LDO2 = OFF, Vdd_alive = ON 40 60
IVCC(PWM) Current into VCC; PWM All 3 DCDC converters enabled & running in PWM, LDOs off VCC = 3.6V 2 mA
PWM DCDC1 and DCDC2 converters enabled and running in PWM, LDOs off 1.5 2.5
PWM DCDC1 converter enabled and running in PWM, LDOs off 0.85 2
Iq Quiescent current All converters disabled, LDO1, LDO2 = OFF, Vdd_alive = OFF VCC = 3.6V 16 μA
All converters disabled, LDO1, LDO2 = OFF, Vdd_alive = ON 26
VLDO1 AND VLDO2 LOW DROPOUT REGULATORS
I(q) Operating quiescent current Current per LDO into VINLDO 16 30 μA
I(SD) Shutdown current Total current into VINLDO, VLDO = 0V 0.6 2 μA
VI Input voltage range for LDO1, LDO2 1.5 6.5 V
VO LDO1 output voltage range 1 3.3 V
LDO2 output voltage range 1 3.3 V
VFB LDO1 and LDO2 feedback voltage 1.0 V
IO Maximum output current for LDO1, LDO2 VI = 1.8V, VO = 1.3V 200 mA
IO Maximum output current for LDO1, LDO2 VI = 1.5V; VO = 1.3V 120 mA
ISC LDO1 and LDO2 short circuit current limit VLDO1 = GND, VLDO2 = GND 400 mA
Minimum voltage drop at LDO1, LDO2 IO = 50mA, VINLDO = 1.8V 120 mV
Minimum voltage drop at LDO1, LDO2 IO = 50mA, VINLDO = 1.5V 65 150 mV
Minimum voltage drop at LDO1, LDO2 IO = 200mA, VINLDO = 1.8V 300 mV
Output voltage accuracy for LDO1, LDO2 IO = 10mA –2% 1%
Line regulation for LDO1, LDO2 VINLDO1,2 = VLDO1,2 + 0.5V (min. 2.5V) to 6.5V, IO = 10mA –1% 1%
Load regulation for LDO1, LDO2 IO = 0mA to 200mA –1% 1%
Regulation time for LDO1, LDO2 Load change from 10% to 90% 10 μs
VDD_ALIVE LOW DROPOUT REGULATOR
Vdd_alive Vdd_alive LDO output voltage, TPS6502500 to TPS6502504 IO = 0mA 1.0 V
IO Output current for Vdd_alive 30 mA
I(SC) Vdd_alive short circuit current limit Vdd_alive = GND 100 mA
Output voltage accuracy for Vdd_alive IO = 0mA –1% 1 %
Line regulation for Vdd_alive VCC = Vdd_alive + 0.5 V to 6.5 V, IO = 0mA –1% 1 %
Regulation time for Vdd_alive Load change from 10% to 90% 10 μs
ANALOGIC SIGNALS DEFDCDC1, DEFDCDC2, DEFDCDC3
VIH High level input voltage 1.3 VCC V
VIL Low level input voltage 0 0.1 V
IH Input bias current 0.001 0.05 μA
THERMAL SHUTDOWN
TSD Thermal shutdown Increasing junction temperature 160 °C
Thermal shudown hysteresis Decreasing junction temperature 20 °C
INTERNAL UNDER VOLTAGE LOCK OUT
UVLO Internal UVLO VCC falling –3% 2.35 3% V
VUVLO_HYST internal UVLO comparator hysteresis 120 mV
VOLTAGE DETECTOR COMPARATOR
PWRFAIL_SNS Comparator threshold Falling threshold –2% 1.0 2% V
Hysteresis 40 50 60 mV
Propagation delay 25mV overdrive 10 μs
VOL Power fail output low voltage IOL = 5 mA 0.3 V