SLVS843B December   2008  – May 2018 TPS650250

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Detailed Block Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Dissipation Ratings
    6. 6.6  Electrical Characteristics
    7. 6.7  Electrical Characteristics VDCDC1
    8. 6.8  Electrical Characteristics VDCDC2
    9. 6.9  Electrical Characteristics VDCDC3
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Step-Down Converters, VDCDC1, VDCDC2 AND VDCDC3
      2. 7.3.2 Power Save Mode Operation
      3. 7.3.3 Soft Start
      4. 7.3.4 100% Duty Cycle Low Dropout Operation
      5. 7.3.5 Low Dropout Voltage Regulators
      6. 7.3.6 Undervoltage Lockout
      7. 7.3.7 PWRFAIL
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Typical Configuration For The Samsung Processor S3C6400-533MHz
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Inductor Selection for the DCDC Converters
        2. 8.2.3.2 Output Capacitor Selection
        3. 8.2.3.3 Input Capacitor Selection
        4. 8.2.3.4 Output Voltage Selection
        5. 8.2.3.5 Voltage Change on VDCDC3
        6. 8.2.3.6 Vdd_alive Output
        7. 8.2.3.7 LDO1 and LDO2
        8. 8.2.3.8 Vcc-Filter
      4. 8.2.4 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.8 Electrical Characteristics VDCDC2

VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6V, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VDCDC2 STEP-DOWN CONVERTER
VI Input voltage range, VINDCDC2 2.5 6 V
IO Maximum output current VO = 2.5V 800 mA
ISD Shutdown supply current in VINDCDC2 EN_DCDC2 = GND 0.1 1 μA
RDS(on) P-channel MOSFET on-resistance VINDCDC2 = VGS = 3.6V 140 300 mΩ
ILP P-channel leakage current VINDCDC2 = 6.0V 2 μA
RDS(on) N-channel MOSFET on-resistance VINDCDC2 = VGS = 3.6V 150 297 mΩ
ILN N-channel leakage current VDS = 6V 7 10 μA
ILIMF Forward current limit (P- and N-channel) 2.5V < VINDCDC2 < 6V 1.05 1.16 1.29 A
fS Oscillator frequency 1.95 2.25 2.55 MHz
VDCDC2 Fixed output voltage MODE = 0 (PWM/PFM) 1.8V VINDCDC2 = 2.5V to 6V; 0 mA ≤ IO ≤ 1.6A –2% 2%
2.5V VINDCDC2 = 3V to 6V; 0 mA ≤ IO ≤ 1.6A –2% 2%
Fixed output voltage MODE = 1 (PWM) 1.8V VINDCDC2 = 2.5V to 6V; 0 mA ≤ IO ≤ 1.6A –2% 2%
2.5V VINDCDC2 = 3V to 6V; 0 mA ≤ IO ≤ 1.6A –1% 1%
Adjustable output voltage with resistor divider at DEFDCDC2 MODE = 0 (PWM) VINDCDC2 = VDCDC2 + 0.5V (min 2.5V) to 6V; 0mA ≤ IO ≤ 1.6A –2% 2%
Adjustable output voltage with resistor divider at DEFDCDC2; MODE = 1 (PWM) VINDCDC2 = VDCDC2 + 0.5V (min 2.5V) to 6V; 0mA ≤ IO ≤ 1.6A –1% 1%
Line regulation VINDCDC2 = VDCDC2 + 0.3 V (min. 2.5 V) to 6V; IO = 10mA 0.0 %/V
Load regulation IO = 10mA to 1.6A 0.25 %/A
tSS Soft start ramp time VDCDC2 ramping from 5% to 95% of target value 750 μs
R(L2) Internal resistance from L2 to GND 1 MΩ