SLVS710C January   2007  – February 2017 TPS65050

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Options
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Dissipation Ratings
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1  Operation of DCDC Converters
        1. 8.3.1.1 DCDC1 Converter
        2. 8.3.1.2 DCDC2 Converter
      2. 8.3.2  Power-Save Mode
      3. 8.3.3  Dynamic Voltage Positioning
      4. 8.3.4  Soft Start
      5. 8.3.5  100% Duty Cycle Low Dropout Operation
      6. 8.3.6  Undervoltage Lockout
      7. 8.3.7  Mode Selection
      8. 8.3.8  Enable
      9. 8.3.9  RESET
      10. 8.3.10 Push-Button ON-OFF (PB-ON-OFF)
      11. 8.3.11 Short-Circuit Protection
      12. 8.3.12 Thermal Shutdown
      13. 8.3.13 Low Dropout Voltage Regulators
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Voltage Setting
          1. 9.2.2.1.1 Converter 1 (DCDC1)
          2. 9.2.2.1.2 Converter 2 (DCDC2)
        2. 9.2.2.2 Output Filter Design (Inductor and Output Capacitor)
          1. 9.2.2.2.1 Inductor Selection
          2. 9.2.2.2.2 Output Capacitor Selection
          3. 9.2.2.2.3 Input Capacitor Selection
        3. 9.2.2.3 Low Drop Out Voltage Regulators (LDOs)
        4. 9.2.2.4 PB-ONOFF and Sequencing
        5. 9.2.2.5 RESET
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resource
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

TPS65050 RSM Package
32-Pin VQFN With Exposed Thermal Pad
Top View
TPS65052 RSM Package
32-Pin VQFN With Exposed Thermal Pad
Top View
TPS65051, TPS65054, TPS65056 RSM Package
32-Pin VQFN With Exposed Thermal Pad
Top View

Pin Functions

PIN I/O DESCRIPTION
NAME TPS65050 TPS65051
TPS65054
TPS65056		 TPS65052
AGND 2 2 2 I Analog GND, connect to PGND and thermal pad
BP 1 1 1 I Input for bypass capacitor for internal reference.
DEFDCDC2 17 17 17 I TPS65050 and TPS65051 devices: Feedback pin for converter 2. Connect DEFDCDC2 to the center of the external resistor divider.
TPS65052 and TPS65056 devices: Select pin of converter 2 output voltage.
High = 1.3 V, Low = 1 V
TPS65054 device: Select pin of converter 2 output voltage.
High = 1.05 V, Low = 1.3 V
DEFLDO1 31 — 31 I Digital input, used to set the default output voltage of LDO1 to LDO4; LSB
DEFLDO2 6 — 6 I Digital input, used to set the default output voltage of LDO1 to LDO4.
DEFLDO3 9 — 9 I Digital input, used to set the default output voltage of LDO1 to LDO4.
DEFLDO4 13 — 13 I Digital input, used to set the default output voltage of LDO1 to LDO4; MSB
EN_DCDC1 25 25 25 I Enable Input for converter 1, active high
EN_DCDC2 26 26 26 I Enable Input for converter 2, active high
EN_LDO1 27 27 27 I Enable input for LDO1. Logic high enables the LDO, logic low disables the LDO.
EN_LDO2 28 28 28 I Enable input for LDO2. Logic high enables the LDO, logic low disables the LDO.
EN_LDO3 15 15 15 I Enable input for LDO3. Logic high enables the LDO, logic low disables the LDO.
EN_LDO4 16 16 16 I Enable input for LDO4. Logic high enables the LDO, logic low disables the LDO.
FB1 — 31 — I Feedback input for the external voltage divider.
FB2 — 6 — I Feedback input for the external voltage divider.
FB3 — 9 — I Feedback input for the external voltage divider.
FB4 — 13 — I Feedback input for the external voltage divider.
FB_DCDC1 24 24 24 I Input to adjust output voltage of converter 1 between 0.6 V and VI. Connect external resistor divider between VOUT1, this pin, and GND.
GND 8 — — — Connect to GND
HYSTERESIS -- 8 8 I Input for hysteresis on reset threshold
L1 22 22 22 O Switch pin of converter 1. Connected to Inductor .
L2 20 20 20 O Switch Pin of converter 2. Connected to Inductor.
MODE 32 32 32 I Select between Power Safe Mode and forced PWM Mode for DCDC1 and DCDC2. In Power Safe Mode, PFM is used at light loads, PWM for greater loads. If PIN is set to high level, forced PWM Mode is selected. If Pin has low level, then the device operates in Power Safe Mode.
PB_IN 7 — — I Input for the pushbutton ON-OFF function
PB_OUT 14 — — O Open-drain output. Active low after the supply voltage (VCC) exceeded the undervoltage lockout threshold. The pin can be toggled pulling PB_IN high.
PGND1 23 23 23 I GND for converter 1
PGND2 19 19 19 I GND for converter 2
RESET — 14 14 O Open-drain active low reset output, 100-ms reset delay time.
THRESHOLD — 7 7 I Reset input
VCC 3 3 3 I Power supply for digital and analog circuitry of DCDC1, DCDC2 and LDOs. This pin must be connected to the same voltage supply as VINDCDC1/2.
VDCDC2 18 18 18 I Feedback voltage sense input, connect directly to the output of converter 2.
VINDCDC1/2 21 21 21 I Input voltage for VDCDC1 and VDCDC2 step-down converter. This must be connected to the same voltage supply as VCC.
VINLDO1 29 29 29 I Input voltage for LDO1
VINLDO2 4 4 4 I Input voltage for LDO2
VINLDO3/4 11 11 11 I Input voltage for LDO3 and LDO4
VLDO1 30 30 30 O Output voltage of LDO1
VLDO2 5 5 5 O Output voltage of LDO2
VLDO3 10 10 10 O Output voltage of LDO3
VLDO4 12 12 12 O Output voltage of LDO4
Thermal pad — — — — Connect to GND