SLVS950I July 2009 – May 2018 TPS65070 , TPS65072 , TPS65073 , TPS650731 , TPS650732
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
DEFSLEW | B7 | B6 | B5 | B4 | B3 | B2 | B1 | BO |
---|---|---|---|---|---|---|---|---|
Bit name and function | SLEW2 | SLEW1 | SLEW0 | |||||
Default | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 |
Default value loaded by: | UVLO | UVLO | UVLO | |||||
Read/write | R | R | R | R | R | R/W | R/W | R/W |
The DEFSLEW register defines the slew rate of the output voltage for DCDC2 and DCDC3 in case the voltage is changed during operation. In case Bit “LDO2 tracking“ in register DEFLDO2 is set, this is also valid for LDO2. When the voltage change is initiated by toggling pin DEFDCDC2 or DEFDCDC3, the start of the voltage change is triggered by the rising or falling edge of the DEFDCDC2 or DEFDCDC3 pin. If a voltage change is done internally be re-programming register DEFDCDC2_LOW, DEFDCDC2_HIGH, DEFDCDC3_LOW or DEFDCDC3_HIGH, the voltage change is initiated immediately after the new value has been written to the register with the slew rate defined.
SLEW2 | SLEW1 | SLEW0 | VDCDC3
SLEW RATE |
---|---|---|---|
0 | 0 | 0 | 0.11 mV/µs |
0 | 0 | 1 | 0.22 mV/µs |
0 | 1 | 0 | 0.45 mV/µs |
0 | 1 | 1 | 0.9 mV/µs |
1 | 0 | 0 | 1.8 mV/µs |
1 | 0 | 1 | 3.6 mV/µs |
1 | 1 | 0 | 7.2 mV/µs |
1 | 1 | 1 | Immediate |