SLVSCF4 Data sheet

SLVSCF4A December 2014 – July 2016 TPS650830

PRODUCTION DATA.

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Mechanical Data (Package|Pins)

ZCG|159
- MPBGAJ2
ZAJ|168
- MPBG703D

Thermal pad, mechanical data (Package|Pins)

Orderable Information

6 Detailed Description

6.1 Overview

The TPS650830 is a single-chip solution Power Management IC designed specifically for the latest Intel Processors targeted for Tablets, Ultrabooks, and Notebooks with NVDC or non-NVDC power architectures, using 2S, 3S, or 4S Lithium-Ion battery packs.

The TPS650830 is used for Volume systems with the low voltage rails merged for the smallest footprint and lowest cost system power solution.

The TPS650830 can provide the complete power solution based on the Intel Reference Designs. Five highly efficient step-down voltage regulators (VRs) and a sink/source LDO, are used along with power-up sequence logic managing external load switches to provide the proper power rails, sequencing, and protection - including DDR3 and DDR4 memory power. The regulators support dynamic voltage scaling (DVS) for maximum efficiency including Connected Standby. The high frequency voltage regulators use small inductors and capacitors to achieve a small solution size. Output power is adjustable on four VR controllers. An I²C interface allows simple control by the embedded controller (EC). Each version is available in a 7x7 NFBGA package and a 9x9 NFBGA package. The 7x7 NFBGA package can be used in Type 4 PCB boards for the smallest area implementation. The 9x9 NFBGA package can be used in Type 3 and Type 4 PCB boards allowing to minimize cost and area.

The Powergood Comparator Logic allows controlling and monitoring up to eight external load switches within the sequence. All the VR and Load Switch Powergood signals are used in the Powergood Tree of which the outputs are shown with open-drain outputs. Enable inputs allow connecting externally to set the sequence, and it also allows using various Sleep Mode State signals. The STANDBYZ allows entering a Deep Sleep Mode, in which the out put voltages of the voltage regulators can be reduced to save power by DVS.

The Power Monitoring comparators are used to detect and monitor up to three input power sources (adapter, battery1, battery2, or any other combination). Over temperature of the PMIC self-protects, and outputs a Status output, TEMPALERTZ; plus there is a dedicated comparator that can monitor system over temperature with multiple stacked PTC thermistors, or an NTC thermistor. The PMIC automatically switches between an internal 3.1-V LDO when a power source is connected; or to a Backup Battery (Coin Cell) when all power sources are removed. This output RTC rail is used to maintain the always-on RTC rails for critical register data.

6.2 Functional Block Diagram

TPS650830 TPS650830_SLVSCF4_block_diagram.gif

6.3 Feature Description

6.3.1 Voltage Regulator Assignment and Powergood Comparator Logic Assignment (External Voltage Regulator or Load Switch) for Skylake and Kabylake Platform

For the Skylake and Kabylake Power Map implementation, the five PMIC voltage regulators and LDO1 are assigned with the low -voltage rails merged or split according to the configuration. For the Volume (merged low voltage rails) configuration six external load switches are controlled and monitored by using six powergood comparator logic blocs.

Table 6-1 Voltage Regulator and Powergood Comparator Logic Assignment for Skylake and Kabylake Platforms

TPS650830	Skylake and Kabylake PLATFORM POWER SYSTEM VOLTAGE RAIL VOLUME (Merged Low Voltage Rails)	OUTPUT VOLTAGE, V_out DEFAULT, or COMPARATOR INPUT	SWITCHING FREQUENCY, F_sw NVDC# = 1 / 0	LPM VOLTAGE, V_out DEFAULT	POWER GOOD OUTPUT SETTING, (PGVRx or PGx is PP or OD)
VR1	V1.00A / V0.85A	1.00 V	500 kHz / 800 kHz	LPM = 1.00 V	PP
VR2	V1.8A	1.8 V	2 MHz / 2 MHz	LPM = 1.8 V	PP
VR3	V3.3A_DSW	3.3 V	800 kHz / 800 kHz	LPM = 3.3 V	PP
VR4	V1.2U	1.2 V,1.35 V,1.1 V	500 kHz / 800 kHz	LPM = 1.2 V,1.35 V,1.1 V	OD
VR5	V5A_DS3	5 V	800 kHz / 800 kHz	LPM = 5.0 V	PP
LDO1	V0.6Dx	0.6 V, 0.675 V, 0.55 V	-	LPM = DDR_VTT_CTRL = Off	NA
External VR_a	none	-	-	-	NA
External VR_b	none	-	-	-	NA
Powergood Comparator Logic a	V3.3A_PCH Enable/Sense External Load Switch	3.3 V, Comparator Analog Input	–	–	PP
Powergood Comparator Logic b	V1.8U_2.5U Enable/Sense External Load Switch	1.8 V, Comparator Analog Input	–	–	PP
Powergood Comparator Logic c	Generic Comparator	-	–	–	--
Powergood Comparator Logic d	VCCIO Enable/Sense External Load Switch	1.00 V, Comparator Analog Input	–	–	PP
Powergood Comparator Logic e	V3.3S Sense External Load Switch	3.3 V, Comparator Analog Input	–	–	PP
Powergood Comparator Logic f	V1.8S Sense External Load Switch	1.8 V, Comparator Analog Input	–	–	PP
Powergood Comparator Logic g	V1.0S Sense External Load Switch	1.00 V, Comparator Analog Input	–	–	OD

6.3.2 Generic Powergood Window Comparator with Open-Drain Output

The generic powergood comparator monitors the output voltage to ensure it is within ±10% of the nominal target voltage there is a 30-µs deglitch on both rising and falling edges of all comparators (converter, controller, comparators). The open-drain output requires an external pull-up resistor - typically in the 100-kΩ range. Open-Drain outputs can be combined to create an "AND" logic function.

Figure 6-1 Generic Powergood Window Comparator with Open-Drain Output

6.3.3 Powergood Window Comparator

All the powergood comparators (converter, controller, comparators) can be configured for either Open-Drain outputs or Push-Pull outputs.

All the powergood comparators (converter, controller, comparators) in analog configuration monitors the output voltage to ensure it is within ±10% of the nominal target voltage. A 30-µs deglitch exists on the output of all the powergood comparators (converter, controller, comparators). The open-drain output requires an external pull-up resistor - typically in the 100-kΩ range. Open-Drain outputs can be combined to create an "AND" logic function. The push-pull output internally pulls up to VDDIO pin rail, or other noted input rail. Care should be taken to minimize series impedance on the PCB and providing adequate bulk and decoupling capacitance for the load switch rails. The Intel Skylake and Kabylake specification is ±5% at each rail, including those provided by load switches, therefore the load switch rails are still protected for ±10% powergood, as required by Intel Skylake and Kabylake specification.

Figure 6-2 Powergood Window Comparator with Open-Drain Output

Figure 6-3 Powergood Window Comparator with Push-Pull Output

6.3.4 3.3-V LDO and 3V3SW Load Switch

The LDO3V powers up when Vin_LDO3V pin goes above the UVLO3V threshold. The LDO3V powers the internal digital blocks and analog blocks of the PMIC. It is also used as the positive rail of the powergood comparator and level-shifter outputs. The 3V3 load switch is optional to connect or disconnect the VOUT3V3SW output to a load. The load switch is enabled by the EN3V3SW pin.

Figure 6-4 LDO3V and 3V3SW Load Switch

6.3.5 5-V LDO and 5VSW Load Switch

The LDO5V powers up when Vin pin goes above the UVLO5V threshold. The LDO5V powers the gate drives for all the five VRs of the PMIC. The 5-V load switch is used to switch the gate drive source from the internal LDO5V LDO to the 3.3-V PWM VR output as soon as the 3.3-V VR powergood signal indicates it is good. This significantly improves the efficiency of the VRs whose effect is more significant at lower VR load current, and VR input voltage. The load switch is enabled by the EN5VSW pin. Connect the V5A_PG signal to the EN5VSW pin. When the EN5VSW pin is high, the LDO5V internal reference drops to 4.5 V to ensure the 5-V VR drives all the gate drive current, but also ensures the gate drive never falls below 4.5 V. When EN5VSW is low, the LDO resumes to 5-V internal reference and the load switch is turned off to disconnect the 5-V VR.

Figure 6-5 5-V LDO and 5VSW Load Switch

6.3.6 RTC Selector and 3.1-V LDO

The RTC selector is used to select between the coincell backup battery or the internal 3.3-V LDO to power the 3P3A_RTC output rail for the RTC domain rail. If the Vin is below the UVLo5V threshold, the coincell battery is selected. If the Vin is greater than the UVLO5V, then the internal 3.1-V LDO is selected. The backup battery selector logic has a very low current draw when battery is selected to extend the charge life of the backup battery. This rail allows keeping the RTC registers' data even when the adapter and main battery is removed from the system. If the coincell voltage falls below the minimum threshold, the RTC registers will be reset to the default values. The 3.1-V LDO is at 3.1 V to ensure the PCH voltage is always below 3.2 V maximum to protect the PCH.

Figure 6-6 RTC Selector and 3.1-V LDO

6.3.7 Power Path Comparators

The Power Path comparators are high voltage comparators rated at 28 V both input and output that are independent of the rest of the PMIC. These can be used even when the PMIC is powered down, as long as the VINPP pin is above the UVLO5V threshold. Connect a resistor divider from the source to set the 1.25-V trigger threshold. These comparators can be used to detect adapter, and up to two batteries. An open-drain pin can detect the status, and a status register detects the status, that can issue an interrupt to the EC. The high voltage rated outputs can be used to turn on external P-channel power MOSFETs to control the power source path. A diode "OR" connection from all the power sources used is recommended to ensure the VINPP is up when a source is available. If these comparators are not used tie the VINPP pin to VIN and VIN_LDO3. Do not ground the VINPP pin when the VIN pin is powered up. These comparators can also be used a general purpose comparators.

Figure 6-7 Power Path Comparators

6.3.8 UVLO Comparators

The UVLO comparators are high voltage comparators rated at 28-V input are powered by the VIN pin for LDO5V and 1.25-V LDO, and the VIN_LDO3V pin for th LDO3V. The VDCSNS input is also a high voltage input pin to detect if VBATA is above a programmable voltage. The Vin and VIN_LDO3 pin are tied directly to VBATA, while the VDCSNS pin requires a resistor divider to set the proper detection gain.

Figure 6-8 UVLO Comparators

6.3.9 Temperature Comparator

The temperature comparator is used to detect either several PTC thermisters stacked in series string, or a single NTC thermister. The PTC thermisters allow an inexpensive overtemperature detection of any fault throughout several points on the motherboard with each PTC thermister selected to have its own temperature threshold trigger point. An internal current source can be enabled to drive the PTC thermisters to minimize noise sensitivity. The current source can be disabled to drive with a voltage source such as the LDO3V to allow a tighter accuracy. Only a single NTC thermister can be detected at a time, but the NTC allows tracking several temperature profiles. This comparator can also be used as a general purpose comparator.

Figure 6-9 Temperature Comparator

6.3.10 Low Power Mode (LPM) / Connected Standby / Instant Go of VRs

All the Voltage regulators from the PMIC can be programmed by register to change the voltage in active mode, or to change to a lower voltage or decay in the low power mode. This can be used to save system power and extend battery life. And such capability is useful to meet the Connected Standby and Instant Go specifications. The STANDBYZ pin triggers low power mode (LPM) when low. The STANDBYZ triggers active mode (not in LPM) when high. Connect the SLP_S0# signal from the PCH to the STANDBYZ pin to trigger the low power mode, LPM. The default settings can be changed by the user with the I²C register at any time.

TPS650830 17_Connected_Standby_InstantGO_VRs.gif

Figure 6-10 Low Power Mode (LPM) / Connected Standby / Instant Go of VRs

Figure 6-11 Dynamic Voltage Scaling (DVS) Transition Timing

The DVS Timing is controlled by the stepping the internal reference down/up. The total ramp down/up transition time is equal to the step time times the number of steps. The number of steps is equal to [(the VOUT_hi voltage minus the VOUT_lo voltage) divided by 25 mV per step]. The step time of 5 µs per 25-mV step ensures a time less than 70 µs for a 300-mV voltage change. The Controller is forced in PWM from the STANDBY# (LPM) transition until 10 µs after the reference ramp down/up ends. This helps ensure a fast response. Likewise the Powergood signal for that rail is masked from the STANDBY# (LPM) transition until 100 µs after the internal reference ramp down/up ends. This ensures there is no false powergood fault turn-off during DVS. In most cases undershoot/overshoot is negligible.

6.3.11 Enable and Powergood of VRs

The VRs are enabled by the ENVRx pins. The powergood is output on the PGVRx pins. The powergood pins can be defined as open-drain or push-pull output, depending on the function in order to allow "ANDing" or to reduce external components and quiescent current. there is a 30-µs deglitch on both edges of the powergood comparator outputs. A status register monitors the powergood outputs, and the powergood tree monitors the powergood for proper sequence and protection. The powergood signals can be masked by a register.

Figure 6-12 Enable and Powergood of VRs

6.3.12 VR4 VDDQ and LDO1 VTT Enabling

The VDDQ is enabled by the ENVR4 pin, while the LDO1 VTT push-pull LDO is enabled by the DDR_VTT_CTRL pin. The DDR_VTT_CTRL pin is often connected to the SLP_S0# pin to turn off during sleep mode. The DDRID pin is a tri-level pin that sets the VR4 VDDQ voltage to either 1.2 V, 1.35 V, or 1.1 V. DDR_VTT_CTRL pin ais also used for DVS control of VR4, as defined on register 0x36, V1P2UCNT.

Figure 6-13 VR4 VDDQ and LDO1 VTT Enabling

6.3.13 Converters

The PMIC has 5 built in DCDC converters. The voltage regulators are highly configurable both in terms of voltage and current. Of the five voltage regulators, four voltage regulators have an external power stage, with programmable current limit (programmed by an external resistor), which allows optimal selection of external passive components based on desired system load. VR2 has a completely integrated power stage, except for the required passive components. To maintain high efficiency, the converters are implemented as synchronous step down converters.

One additional voltage regulators in the form of Low Drop Out (LDO) linear regulators are integrated as part of the PMIC. One of the LDOs, LDO1, is capable of sinking and sourcing current that regulates from the step down controller (for DDR memory). This LDO is designed to specifically provide the VTT power to DDR memory. Its output voltage tracks the output voltage of the step down controller and is set to regulate to half of the step down controller voltage.

6.3.13.1 Power Save Mode

At medium and heavy loads, the converter and the controllers operate in a PWM mode. As soon as the inductor current gets discontinuous, which means that the output current gets lower than half of the inductor ripple current, the converters enter Power Save Mode. In Power Save Mode the switching frequency decreases linearly with the load current and maintains a high efficiency. By default, the converters and controller operate in the AutoPFM mode such that the transition into and out of Power Save Mode happens within the entire regulation scheme and is seamless in both directions.

Figure 6-14 PFM and PWM Mode Operation

The figure above shows the converter/ controller operation in PFM and PWM mode. In PFM mode the minimum voltage that the output falls to is the programmed regulation voltage. The output voltage ripple in PFM mode is determined based on the external passive components (L and C). The regulator ensures that the minimum voltage during PFM mode is the same as the programmed regulation voltage (within the AC and DC tolerance).

TPS650830 24_16_pulse_CCM_to_DCM_Transition_2.gif

Figure 6-15 Operation During Load Step Transient: CCM to DCM Transition and DCM to CCM Transition

The figure above shows the inductor current of the controller during a load transient as it transitions in and out of Continuous Conduction Mode (CCM) and Discontinuous Conduction Mode (DCM). CCM is often referred to as pulse width modulation (PWM) mode, and DCM is referred to as pulse frequency mode (PFM) mode. When the load step falls, there is a 16 cycle deglitch going from CCM to DCM. This allows a fast transient response and tighter peak to peak ripple voltage. When the load step rises, there is no deglitch time, so the controller goes directly from DCM to CCM in a quick response characteristic of CCM. The VR1, VR3, VR4, and VR5 controllers have the CCM to DCM 16 cycle count deglitch enabled.

6.3.13.2 Voltage Regulator Startup

All the voltage regulators including the VTT LDO1 can be enabled using either pin enables or I²C commands. The default setting uses the pin enable. The VTT LDO1 can only be enabled using the DDR_VTT_CTRL discrete input. VTT LDO1 can be enabled by pin (DDR_VTT_CTRL) or by register (0xE9, MSB bit 7 masks the DDR_VTT_CTRL pin, and bit 6 enables the VTT LDO1). Each Voltage Regulator (VR) can be enabled by the enable pin (ENAVRx) or by I²C Register (xCNT). The voltage should not be changed by register at the exact same time the voltage regulator is enabled. If a different voltage than the default is needed at power-up, then the register (xCNT) should program the voltage first, and then a separate command should enable the register separately. Dynamic voltage change (DVS) can be done any time after power-up.

Each of the voltage regulators except for the VTT LDO1 are controlled by an internal softstart to make sure the output voltage ramps up gently and does not cause huge inrush current during startup to prevent droop on the input. The VTT LDO1 startup time is driven by the DDR memory requirements for the VTT voltage rail - which requires that the ramp up on voltage be faster than 35 µs.

6.3.13.3 Powergood, Power Fault, and Emergency Power Shutdown

During operation, when the voltage regulators are enabled, the output voltage for each rail is monitored in order to assess if the output voltage is within a specified voltage range. A powergood status bit is generated and stored in the PGOOD_STAT1 and PGOOD_STAT2 registers. If the output voltage is within the specified voltage range, the respective powergood status bit is set to a logic high. If the output voltage falls below or goes above the specified voltage range, the powergood status bit will be set to a logic low.

By default, if any of the output voltage rails experience a power fault condition, the PMIC will automatically shutdown in order to protect the system unless the power fault is masked. If a power fault occurs, the source of the power fault is maintained in the PWRSTAT1 and PWRSTAT2 registers which are maintained in the RTC domain. The voltage thresholds for each of the powergood comparators is a percentage relative to the nominal voltage setting of the output voltage - see the parametric table for each voltage regulator powergood for the USL and LSL limits of the powergood comparators.

If a particular voltage rail is not critical to the performance of the overall system, the respective powergood output can be masked using the PGMASK1 and PGMASK2 registers. The masking of a power fault will inhibit an automatic PMIC shutdown. This can be also very helpful for debug purposes in case of system failure to isolate the voltage regulator with the sensitive output voltage.

In order to avoid an erroneous power fault during the turn-on of the voltage regulators, the power fault is masked for 10 ms relative to the enable whether it be from the discrete signal or from an I²C command. powergood is also masked when coming out of sleep (S3 state) for 100 µs after the ALL_SYS_PWRGD pin goes high to ensure that there is no false triggering of the powergood comparators.

The PMIC will only cause a Emergency Power Shutdown of the rails for the conditions shown in the table below. The PMIC monitors each rail and ensures there is no problem. All rails are monitored for fault protection, except for V3.3A_DSW and V5A external voltage regulators. The V3.3A_DSW and V5A have no effect on Power Fault and cannot cause a shutdown, unless either one affects another rail. Notice also, that the current limit (OCP) does not directly cause a shutdown. Instead, OCP could cause a shutdown indirectly by means of a Power Fault. The OCP will limit the maximum possible output current, such that if the load current exceeds the Ilim, then the voltage will drop, until eventually the lower output voltage causes a Power Fault if it is below the powergood threshold for more than 30 µs. Emergency Power Shutdown causes all rails to power-down within 1 us. The LDO3, LDO5, and VREF1.25V will stay up if the input voltage is greater than the UVLO3 and UVLO5.

Table 6-2 All Possible Emergency Power Shutdown Conditions

SHUTDOWN CONDITION
VIN pin ≤ UVLO5V
VINLDO3 pin ≤ UVLO3V
Powergood Fault (OVP, UVP): Vout ≤ 90% or Vout ≥ 110% for ≥ 30 µs
Tj ≥ Tcritical (OTP)
SHUTDOWNZ pin pulled-low
I²C Control Force Shutdown by SDWNCTRL register (address = 0x49)

6.3.13.4 Current Limit

All voltage regulators are current limited, the current limit can be set based on the application load current using an external resistor for all VRs except for VR2 which has an internally set current limit as it has an integrated power stage. The current limit controls the maximum output current. If the maximum current is reached, the output voltage will start to droop since the load can no longer be supplied with sufficient power. If the voltage drops below the powergood threshold, the power fault status will be set to a logic high and if the power fault is not masked, the PMIC will automatically shutdown in a controlled manner to protect the system.

6.3.13.5 Output Discharge Feature

All the voltage regulators have a built in output discharge feature. The output discharge feature consists of being able to configure register bits to enable a discharge resistor which is only active whenever the voltage regulator is disabled. The discharge resistors for each of the voltage regulators can be configured using the DISCHCNT1, DISCHCNT2, DISCHCNT3 and DISCHCNT4 registers. The discharge resistors are disconnected when the voltage regulators are enabled in order to minimize any losses within the PMIC.

6.3.13.6 Output Voltage Control

All voltage regulators are designed to regulate a fixed output voltage. To achieve high accuracy the output voltage for the converters and controller is sensed using a separate feedback pin. For each of the voltage rails, except for the VTT LDO, the output voltage can be changed to slightly higher or lower values by changing the default setting in the voltage regulator control registers (see section on the Voltage Regulator Voltage Options). This function can be used to save power when supplying the connected load at its minimum possible supply voltage or to compensate for voltage drops during load transients by programming it slightly higher. In addition the range of the output voltage for the regulators is highly programmable. If you need a different output voltage configuration from the specified default, please contact TI to generate you a custom part.

6.3.13.7 Converter Low Power Mode Operation

For optimizing low power operation, the output voltage of the converters can be set to a specific value. The low power output voltage is set by the specific register and bits shown in the Voltage Regulator Voltage Options tables. Entering the low power mode is accomplished by asserting the SLP_S0# signal to a logic low. In this low power mode, the powergood function remains active and is not affected by the transition from normal operation mode to the low power mode and vice versa.

6.3.13.8 Controller Low Power Mode Operation

For optimizing low power operation, the output voltage of the controllers can be set to a specific value. The low power output voltage is set by the specific register and bits shown in the Voltage Regulator Voltage Options tables. Entering the low power mode is accomplished by asserting the DDR_VTT_CTRL pin or the STANDBYZ pin to a logic low. In this low power mode, the powergood function remains active and is not affected by the transition from normal operation mode to the low power mode and vice versa. DDR_VTT_CTRL pin asserts DVS on VR4, while STANDBYZ pin asserts DVS in VR1, VR2, VR3, and VR5, as defined by ther CNT registers. In situations where the output current demand from the controller is very small, the controller is automatically placed in an Ultra Low Quiescent (ULQ) mode to reduce power consumption and increase the efficiency.

6.3.13.9 Controller Internal Ramp Comparator

The controllers have an internal ramp, characteristic of th DCAP2 control architecture, to give improved performance with low-ESR output capacitors. This internal ramp provides ramp compensation that helps maintain a relatively constant frequency during CCM, and it provides better stability for designs with very low ESR on the output capacitors. The ramp height can be optimized and is a function of the input voltage to provide proportional feed-forward. At very high voltages, the ramp may exceed the operating window of the PWM comparator and may overpower the natural ripple of the output, so there is a need to switch to a smaller ramp. As the ramp was already getting large, it helps to switch back to a smaller size. To achieve this, a comparator monitors the input voltage at the VIN pin. When input voltage rises and exceeds 11 V, it changes the ramp to a slightly smaller value. There is a wide 1.1-V hysteresis, so at approximately 9.9 V as the Vin falls, the ramp returns to the slightly bigger size. In most cases this difference is negligible.

6.3.13.10 Undervoltage Lockout

An undervoltage lockout function prevents the PMIC from operating if the supply voltage on the VIN pin of the PMIC is lower than the undervoltage lockout threshold (see Electrical Characteristics table). During operation, if the supply voltage on the VIN pin drops below the undervoltage lockout threshold, the system/PMIC will shutdown.

6.3.14 Coincell Selector

6.3.14.1 Functional Description of RTC Powerpath and LDO

In case where the main system battery is removed and there is no alternate power source, the RTC data, configuration and status registers, oscillator and timekeeping path of the RTC block are backed up by either a super capacitor or a coin cell battery. If the coincell/ super capacitor battery voltage falls below the minimum operational voltage and there is no input voltage (AC/ DC above the PMIC UVLO), the RTC data registers will be invalid. As the Intel RTC cannot handle a max voltage higher than 3.2 V, when AC/DC is present and is higher than the UVLO threshold, the RTC is supplied by the AC/DC rather than from the coincell - thus maximizing the stored charge in the coincell battery. When AC/DC is present, the internal coincell selector selects the higher of the coincell voltage and the AC/DC voltage. When AC/DC is chosen as a source, there is a coincell LDO which is driven from the 5-V PMIC LDO to regulate The output voltage is fixed at 3.1 V to ensure the maximum voltage is kept below 3.2 V.

The main power source for the RTC LDO is the 5-V PMIC internal LDO, when the main system battery (VDC) is greater than 5.4 V. The RTC LDO will be bypassed and the RTC supply will be powered by the coincell when VDC falls below this threshold - to maximize the coincell battery life. The coincell is used as a last resort. All power routing of the source selection for the RTC power is done internally and no external connections other than the coin cell or super cap is required.

6.4 Device Functional Modes

Figure 6-16 Sequence of Function Modes - Assuming the TPS650830 Application Configuration Connections

6.4.1 OFF State - No VIN and No Backup Battery

If the VIN and the VBATTBKUP battery are both lower than their respective UVLOs then, the device will be in the OFF state. In this state the device will not be able to turn on or enable any VRs or discrete load switches / regulators. The clock and I²C are not active in this state.

In the OFF state, the power path switch comparators, ACIN, BAT1, and BAT2 are the only block available for use. In order to use these comparators the VINPP must be supplied with the highest of the 3 input voltages from AC, BAT1, and BAT2. In all other states the VINPP must be supplied from the same source as VIN.

6.4.2 Startup

The device enters STARTUP once the VIN > UVLO. During STARTUP LDO3V, LDO5V, and VREF1V25 ramp up. Once both LDO3V and LDO5V reach their nominal voltage and their powergoods assert HIGH, the OTP loads into the I²C registers. After the LDO5V_PG asserts HIGH, the RTC LDO is turned on and the V3.3A_RTC is regulated to 3.1 V powered from the LDO5V. Once the OTP is loaded and the RTC is regulated to 3.1 V the device enters READY state.

6.4.3 Ready State

The device is considered to be in the READY state once, all of the internal supplies and RTC are regulated and the OTP is loaded into the registers. In this state the device is ready for enable commands. The comparators, level shifters and all other blocks are available for use.

6.4.4 S5/S4 State

The S5/S4 states are entered when the V3.3A_DSW, V1.8A, V5A_DS3, V3.3A_PCH, V0.85A, and V1.00A are all enabled and regulating with valid powergoods. In this state the RSMRST#_PWRGD will be asserted HIGH.

6.4.5 S3 State

To enter S3 state the SLP_S4# signal must be asserted HIGH. Upon SLP_S4# assertion the VDDQ (VR4), and V1.8U rails are turned on.

6.4.6 S0 State

To enter S0 state the SLP_S3# signal must be asserted HIGH in addition to valid 3.3-V, 1.8-V, and 1.0-V signals on VSE, VSF, and VSG pins. Upon PGG = 1 and PGVR4 = 1 the VCCIO and rail is turned on and the device transitions to S0 state. ALL_SYS_PWRGD asserts HIGH in this state.

6.4.7 Standby

Standby is entered when the STANDBYZ pin transitions from HIGH to LOW provided that ALL_SYS_PWRGD is HIGH. During the STANDBY state the device will DVS and/or decay the VRs that are programmed to DVS or decay from the I²C register definitions, (registers x30 - x38).

6.4.8 DSx State

The DSx state is entered from STARTUP by the enabling of V3.3A_DSW. From the S5/S4 states it can be entered by either pulling the SLP_SUS# signal LOW or writing to VREN, EC_SLP_S4 = EC_DS4 = 1. In this state, the V5A_DS3 and V1.8A may be turned off.

6.4.9 Emergency Shutdown

Emergency Shutdown is a protection feature for the system loads. It reduces the risk of reverse bias in the processor or other devices from once rail to another. Once Emergency Shutdown is initiated the DPWROK pin is pulled LOW, discharge resistors are enabled for all rails, and all rails are disabled at the same time. The PMIC remains in Emergency Shutdown until any of the follow occurs:

PWRBTNIN falling edge detected
ACOK transitions from LOW to HIGH
VIN < UVLO

Emergency Shutdown is initiated when:

VR Fault detected - Read RESETIRQ1 to determine if VR fault caused shutdown.
Hardware force shutdown
Software force shutdown
Die Thermal Fault - Read RESETIRQ2 to determine if thermal fault caused shutdown.
PWRBTN held longer than defined time by FLT[5:0] - Read RESETIRQ1 to determine if push button caused shutdown.
VIN < UVLO - Read IRQLVL1 bit 2 to determine if VIN < UVLO caused shutdown.

6.4.10 Backup Battery / G3 - No VIN

G3 is an Intel defined state where the VIN < UVLO to the device but, a valid backup battery is present on VBATTBKUP pin. In this state, the backup battery is passed to the RTC output and the RTC domain I²C register values are saved. Once the VIN > UVLO these register retain their value and can be read once I²C is ready.

In this state, all VRs and internal LDOs are off and I²C access is not available.

6.5 Programming

6.5.1 I²C - Interface

I²C is a 2-wire serial interface developed by NXP (formerly Philips Semiconductor) (see I²C-Bus Specification and user manual, Rev 4, 13 February 2012). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I²C compatible devices connect to the I²C bus through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on the bus under control of the master device.

The TPS650830 works as a slave and supports the following data transfer modes, as defined in the I²C-Bus Specification: standard mode (100 kbps), fast mode (400 kbps). The interface adds flexibility to the power supply solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements. Register contents are loaded when voltage is applied to TPS650830 higher than the undervoltage lockout threshold. The I²C interface is running from an internal oscillator that is automatically enabled when there is an access to the interface.

The data transfer protocol for standard and fast modes is exactly the same, therefore, they are referred to as F/S-mode in this document.

The TPS650830 supports 7-bit addressing; 10-bit addressing and general call address are not supported. The default device address is defined by the status of the SLAVEADDR pin. 3 different slave addresses are possible, 0x30 (SLAVEADDR 0 V), 0x32 (SLAVEADDR 3.3 V) and 0x34 (SLAVEADDR floating).

All registers are set to their default value when the supply voltage is below the UVLO threshold.

6.5.1.1 F/S-Mode Protocol

The master initiates data transfer by generating a start condition. The start condition is when a high-to-low transition occurs on the SDA line while SCL is high, see Figure 6-17. All I²C-compatible devices should recognize a start condition.

The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires the SDA line to be stable during the entire high period of the clock pulse, see Figure 6-18. All devices recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a matching address generates an acknowledge, see Figure 6-19, by pulling the SDA line low during the entire high period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that the communication link with a slave has been established.

The master generates further SCL cycles to either transmit data to the slave (R/W bit = 0) or receive data from the slave (R/W bit = 1). In either case, the receiver needs to acknowledge the data sent by the transmitter. An acknowledge signal can either be generated by the master or by the slave, depending on which one is the receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as necessary.

To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to high while the SCL line is high, see Figure 6-17. This releases the bus and stops the communication link with the addressed slave. All I²C compatible devices must recognize the stop condition. Upon the receipt of a stop condition, all devices know that the bus is released, and they wait for a start condition followed by a matching address

Attempting to read data from register addresses not listed in this section results in FFh being read out. FS I²C operation does not support repeated start

6.5.1.2 Diagrams of I²C Protocol

Figure 6-17 START and STOP Conditions

Figure 6-18 Bit Transfer on the I²C-bus

Figure 6-19 Acknowledge on the I²C-Bus

Figure 6-20 Bus Protocol

Figure 6-21 I²C Interface WRITE to Device in F/S Mode

Figure 6-22 I²C Interface READ from Device in F/S Mode

6.6 Register Map

Table 6-3 Register Summary

Register Address	Register Name	Domain	Short Description
x00	VENDORID	UVLO	Code that indicated a Texas Instruments' PMIC device.
x01	REVID	UVLO	Code to identify device revision and programming revision.
x02	IRQLVL1	RTC	Top level interrupts
x04	PWRSRCINT	RTC	Input power interrupts
x05	PMUINT	RTC	PMU interrupts
x08	RESETIRQ1	RTC	Emergency Shutdown interrupts
x09	RESETIRQ2	RTC	Emergency Shutdown interrupts
x0B	MPMUINT	RTC	Mask PMU interrupts
x0C	MPWRSRCNT	RTC	Mask input power interrupts
x11	RESETIRQ1MASK	RTC	Mask Emergency Shutdown interrupts
x12	RESETIRQ2MASK	RTC	Mask Emergency Shutdown interrupts
x13	IRQLVL1MSK	RTC	Mask top level interrupt
x14	PBCONFIG	RTC	Power Button configuration
x15	PBSTATUS	RTC	Power Button Status
x16	PWRSTAT1	RTC	VR Fault Reporting
x17	PWRSTAT2	RTC	VR Fault Reporting
x18	PGMASK1	RTC	Mask VR PGs from System Power Good Tree
x19	PGMASK2	RTC	Mask VR PGs from System Power Good Tree
x30	VCCIOCNT	UVLO	VCCIO (PGD ) Control
x31	V5ADS3CNT	UVLO	V5A_DS3 (VR5 ) Control
x32	V33ADSWCNT	UVLO	V3.3A_DSW (VR3 ) Control
x33	V33APCHCNT	UVLO	V3.3A_PCH (PGE) Control
x34	V18ACNT	UVLO	V1.8A (VR2 ) Control
x35	V18U25UCNT	UVLO	V1.8U_2.5U (PGB) Control
x36	V1P2UCNT	UVLO	V1.2U / VDDQ (VR4) Control
x37	V100ACNT	UVLO	V1.00A (VR1) Control
x38	V08ACNT	UVLO	V0.85A (VR1 ) Control
x3B	VRMODECTRL	UVLO	Force Low Power Mode
x3C	DISCHCNT1	UVLO	Discharge Resistors Settings
x3D	DISCHCNT2	UVLO	Discharge Resistors Settings
x3E	DISCHCNT3	UVLO	Discharge Resistors Settings
x3F	DISCHCNT4	UVLO	Discharge Resistors Settings
x40	PWRGDCNT1	UVLO	System Level Power Goods
x41	VREN	UVLO	Deep Sleep Enable
x42	REGLOCK	UVLO	Lock for Control Registers, x30 - x38
x43	VRENPINMASK	UVLO	Mask hardware enable pins
x48	RSTCTRL	RTC	Reset Control
x49	SDWNCTRL	UVLO	Software Force Shutdown
x51	VDLMTCRT	UVLO	VDCSNS Settings
x69	ACOKDBDM	UVLO	ACOK Settings
x6A	LOWBATTDET	UVLO	Battery Detection Settings
x6F	SPWRSRCINT	UVLO	Input power Statuses
xD0	CLKCTRL1	RTC	Clock Control
xDD	COMPA_REF	UVLO	Comparator A Settings
xDE	COMPB_REF	UVLO	Comparator B Settings
xDF	COMPC_REF	UVLO	Comparator C Settings
xE0	COMPD_REF	UVLO	Comparator D Settings
xE1	COMPE_REF	UVLO	Comparator E Settings
xE2	COMPF_REF	UVLO	Comparator F Settings
xE3	COMPG_REF	UVLO	Comparator G Settings
xE4	COMPH_REF	UVLO	Comparator H Settings
xE5	PWRFAULT_MASK1	UVLO	Mask VR Faults from Emergency Shutdown
xE6	PWRFAULT_MASK2	UVLO	Mask VR Faults from Emergency Shutdown
xE7	PGOOD_STAT1	UVLO	VR PGs Statuses
xE8	PGOOD_STAT2	UVLO	VR PGs Statuses
xE9	MISC_BITS	UVLO	Misc. Bits
xEA	STDY_CTRL	RTC	VCOMP and Standby Control
xEB	TEMPCRIT	RTC	VR Critical Temperature
xEC	TEMPHOT	RTC	VR Hot Temperature
xED	OVERCURRENT	RTC	VR Overcurrent
xEE	VREN_PIN_OVR	UVLO	VR Enable Override with Software