SLVSCF4A December   2014  – July 2016 TPS650830

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Simplified System Diagram
  2. 2 Revision History
  3. 3  Device Options
  4. 4 Pin Configuration and Functions
    1. 4.1 Pin Functions
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  6. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Voltage Regulator Assignment and Powergood Comparator Logic Assignment (External Voltage Regulator or Load Switch) for Skylake and Kabylake Platform
      2. 6.3.2  Generic Powergood Window Comparator with Open-Drain Output
      3. 6.3.3  Powergood Window Comparator
      4. 6.3.4  3.3-V LDO and 3V3SW Load Switch
      5. 6.3.5  5-V LDO and 5VSW Load Switch
      6. 6.3.6  RTC Selector and 3.1-V LDO
      7. 6.3.7  Power Path Comparators
      8. 6.3.8  UVLO Comparators
      9. 6.3.9  Temperature Comparator
      10. 6.3.10 Low Power Mode (LPM) / Connected Standby / Instant Go of VRs
      11. 6.3.11 Enable and Powergood of VRs
      12. 6.3.12 VR4 VDDQ and LDO1 VTT Enabling
      13. 6.3.13 Converters
        1. 6.3.13.1  Power Save Mode
        2. 6.3.13.2  Voltage Regulator Startup
        3. 6.3.13.3  Powergood, Power Fault, and Emergency Power Shutdown
        4. 6.3.13.4  Current Limit
        5. 6.3.13.5  Output Discharge Feature
        6. 6.3.13.6  Output Voltage Control
        7. 6.3.13.7  Converter Low Power Mode Operation
        8. 6.3.13.8  Controller Low Power Mode Operation
        9. 6.3.13.9  Controller Internal Ramp Comparator
        10. 6.3.13.10 Undervoltage Lockout
      14. 6.3.14 Coincell Selector
        1. 6.3.14.1 Functional Description of RTC Powerpath and LDO
    4. 6.4 Device Functional Modes
      1. 6.4.1  OFF State - No VIN and No Backup Battery
      2. 6.4.2  Startup
      3. 6.4.3  Ready State
      4. 6.4.4  S5/S4 State
      5. 6.4.5  S3 State
      6. 6.4.6  S0 State
      7. 6.4.7  Standby
      8. 6.4.8  DSx State
      9. 6.4.9  Emergency Shutdown
      10. 6.4.10 Backup Battery / G3 - No VIN
    5. 6.5 Programming
      1. 6.5.1 I2C - Interface
        1. 6.5.1.1 F/S-Mode Protocol
        2. 6.5.1.2 Diagrams of I2C Protocol
    6. 6.6 Register Map
      1. 6.6.1 Registers
        1. 6.6.1.1  VENDORID Register (address = 0x00) [reset = 00100010]
        2. 6.6.1.2  REVID Register (address = 0x01) [reset = 00000000]
        3. 6.6.1.3  IRQLVL1 Register (address = 0x02) [reset = 00000000]
        4. 6.6.1.4  PWRSRCINT Register (address = 0x04) [reset = 00000000]
        5. 6.6.1.5  PMUINT Register (address = 0x05) [reset = 00000000]
        6. 6.6.1.6  RESETIRQ1 Register (address = 0x08) [reset = 00000000]
        7. 6.6.1.7  RESETIRQ2 Register (address = 0x09) [reset = 00000000]
        8. 6.6.1.8  MPMUINT Register (address = 0x0B) [reset = 00010100]
        9. 6.6.1.9  MPWRSRCINT Register (address = 0x0C) [reset = 01111000]
        10. 6.6.1.10 RESETIRQ1MASK Register (address = 0x11) [reset = 00110000]
        11. 6.6.1.11 RESETIRQ2MASK Register (address = 0x12) [reset = 00000010]
        12. 6.6.1.12 IRQLVL1msK Register (address = 0x13) [reset = 10100101]
        13. 6.6.1.13 PBCONFIG Register (address = 0x14) [reset = 00011111]
        14. 6.6.1.14 PBSTATUS Register (address = 0x15) [reset = 00000000]
        15. 6.6.1.15 PWRSTAT1 Register (address = 0x16) [reset = 00000000]
        16. 6.6.1.16 PWRSTAT2 Register (address = 0x17) [reset = 00000000]
        17. 6.6.1.17 PGMASK1 Register (address = 0x18) [reset = 00000000]
        18. 6.6.1.18 PGMASK2 Register (address = 0x19) [reset = 00000000]
        19. 6.6.1.19 VCCIOCNT Register (address = 0x30) [reset = 00001010]
        20. 6.6.1.20 V5ADS3CNT Register (address = 0x31) [reset = 00101010]
        21. 6.6.1.21 V33ADSWCNT Register (address = 0x32) [reset = 00101010]
        22. 6.6.1.22 V33APCHCNT Register (address = 0x33) [reset = 00001010]
        23. 6.6.1.23 V18ACNT Register (address = 0x34) [reset = 00101010]
        24. 6.6.1.24 V18U25UCNT Register (address = 0x35) [reset = 00001010]
        25. 6.6.1.25 V1P2UCNT Register (address = 0x36) [reset = 00111010]
        26. 6.6.1.26 V100ACNT Register (address = 0x37) [reset = 00011010]
        27. 6.6.1.27 V085ACNT Register (address = 0x38) [reset = 00101010]
        28. 6.6.1.28 VRMODECTRL Register (address = 0x3B) [reset = 00111111]
        29. 6.6.1.29 DISCHCNT1 Register (address = 0x3C) [reset = 00000000]
        30. 6.6.1.30 DISCHCNT2 Register (address = 0x3D) [reset = 00000000]
        31. 6.6.1.31 DISCHCNT3 Register (address = 0x3E) [reset = 00000000]
        32. 6.6.1.32 DISCHCNT4 Register (address = 0x3F) [reset = 00000000]
        33. 6.6.1.33 PWRGDCNT1 Register (address = 0x40) [reset = 01011111 ]
        34. 6.6.1.34 VREN Register (address = 0x41) [reset = 00000000]
        35. 6.6.1.35 REGLOCK Register (address = 0x42) [reset = 00000000]
        36. 6.6.1.36 VRENPINMASK Register (address = 0x43) [reset = 00000000]
        37. 6.6.1.37 RSTCTRL Register (address = 0x48) [reset = 00011100]
        38. 6.6.1.38 SDWNCTRL Register (address = 0x49) [reset = 00000000]
        39. 6.6.1.39 VDLMTCRT Register (address = 0x51) [reset = 00000101]
        40. 6.6.1.40 ACOKDBDM Register (address = 0x69) [reset = 00001111]
        41. 6.6.1.41 LOWBATTDET Register (address = 0x6A) [reset = 11111000]
        42. 6.6.1.42 SPWRSRCINT Register (address = 0x6F) [reset = 00000000]
        43. 6.6.1.43 CLKCTRL1 Register (address = 0xD0) [reset = 00000000]
        44. 6.6.1.44 COMPA_REF Register (address = 0xDD) [reset = 00000000]
        45. 6.6.1.45 COMPB_REF Register (address = 0xDE) [reset = 00000000]
        46. 6.6.1.46 COMPC_REF Register (address = 0xDF) [reset = 00000000]
        47. 6.6.1.47 COMPD_REF Register (address = 0xE0) [reset = 00000000]
        48. 6.6.1.48 COMPE_REF Register (address = 0xE1) [reset = 00000000]
        49. 6.6.1.49 COMPF_REF Register (address = 0xE2) [reset = 00000000]
        50. 6.6.1.50 COMPG_REF Register (address = 0xE3) [reset = 00000000]
        51. 6.6.1.51 COMPH_REF Register (address = 0xE4) [reset = 00000000]
        52. 6.6.1.52 PWFAULT_MASK1 Register (address = 0xE5) [reset = 00000000]
        53. 6.6.1.53 PWFAULT_MASK2 Register (address = 0xE6) [reset = 00000000]
        54. 6.6.1.54 PGOOD_STAT1 Register (address = 0xE7) [reset = 00000000]
        55. 6.6.1.55 PGOOD_STAT2 Register (address = 0xE8) [reset = 00000000]
        56. 6.6.1.56 MISC_BITS Register (address = 0xE9) [reset = 00010000]
        57. 6.6.1.57 STDBY_CTRL Register (address = 0xEA) [reset = 11111110]
        58. 6.6.1.58 TEMPCRIT Register (address = 0xEB) [reset = 00000000]
        59. 6.6.1.59 TEMPHOT Register (address = 0xEC) [reset = 00000000]
        60. 6.6.1.60 VREN_PIN_OVR Register (address = 0xEE) [reset = 00000000]
  7. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Controller Design Procedure
          1. 7.2.2.1.1 Selecting the Inductor
          2. 7.2.2.1.2 Selecting the Output Capacitors
          3. 7.2.2.1.3 Selecting the FETs
          4. 7.2.2.1.4 Bootstrap Capacitor
          5. 7.2.2.1.5 Setting the Current Limits
          6. 7.2.2.1.6 Selecting the Input Capacitors
        2. 7.2.2.2 Converter Design Procedure
          1. 7.2.2.2.1 Selecting the Inductor
          2. 7.2.2.2.2 Selecting the Output Capacitors
          3. 7.2.2.2.3 Selecting the Input Capacitors
        3. 7.2.2.3 LDO Design Procedure
        4. 7.2.2.4 Board Temperature Monitoring Design Procedure
        5. 7.2.2.5 Power Path Design Procedure
      3. 7.2.3 Application Performance Curves
      4. 7.2.4 Specific Application - TPS650830 Powering the Intel SkyLake and Kabylake Platform Volume Configuration
        1. 7.2.4.1 Design Requirements
        2. 7.2.4.2 Detailed Design Procedure
          1. 7.2.4.2.1 Output Inductance and Capacitance
        3. 7.2.4.3 Application Performance Curves
    3. 7.3 System Example
    4. 7.4 Do's and Don'ts
  8. 8 Power Supply Recommendations
  9. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Fanout for ZAJ using Type 4 Routing
      2. 9.1.2 Fanout for ZCG using Type 3 Routing
      3. 9.1.3 Layout Checklist
    2. 9.2 Layout Example
      1. 9.2.1 Controller Layout
      2. 9.2.2 ZAJ Package
      3. 9.2.3 ZCG Package
    3. 9.3 Thermal Considerations
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Development Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Community Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Device Options

Table 3-1 Voltage Regulator and Powergood Comparator Logic Assignment for Skylake and Kabylake Platforms

TPS650830 Skylake and Kabylake PLATFORM POWER
SYSTEM VOLTAGE RAIL
VOLUME (Merged Low Voltage Rails) 		OUTPUT VOLTAGE, Vout DEFAULT, or COMPARATOR INPUT SWITCHING FREQUENCY, Fsw
NVDCZ = 1 / 0 		LPM VOLTAGE, Vout
Default 		POWER GOOD OUTPUT SETTING, (PGVRx or PGx is PP or OD)
VR1 V1.00A / V 0.85A 1.00 V 500 kHz / 800 kHz LPM = 1.00 V PP
VR2 V1.8A 1.8 V 2 MHz / 2 MHz LPM = 1.8 V PP
VR3 V3.3A_DSW 3.3 V 800 kHz / 800 kHz LPM = 3.3 V PP
VR4 V1.2U 1.2 V,1.35 V,1.1 V 500 kHz / 800 kHz LPM = 1.2 V,1.35 V,1.1 V OD
VR5 V5A_DS3 5 V 800 kHz / 800 kHz LPM = 5.0 V PP
LDO1 V0.6Dx 0.6 V, 0.675 V, 0.55 V - LPM = DDR_VTT_
CTRL = Off 		NA
External VR_a none - - - --
External VR_b none - - - --
Powergood Comparator Logic a V3.3A_PCH Enable/Sense External Load Switch 3.3 V, Comparator Analog Input – – PP
Powergood Comparator Logic b V1.8U_2.5U Enable/Sense External Load Switch 1.8 V, Comparator Analog Input – – PP
Powergood Comparator Logic c Generic Comparator - Comparator Disabled – – -
Powergood Comparator Logic d VCCIO Enable/Sense External Load Switch 1.00 V, Comparator Analog Input – – PP
Powergood Comparator Logic e V3.3S Sense External Load Switch 3.3 V, Comparator Analog Input – – PP
Powergood Comparator Logic f V1.8S Sense External Load Switch 1.8 V, Comparator Analog Input – – PP
Powergood Comparator Logic g V1.0S Sense External Load Switch 1.00 V, Comparator Analog Input – – OD