SLVSCF4A December   2014  – July 2016 TPS650830

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Simplified System Diagram
  2. 2 Revision History
  3. 3  Device Options
  4. 4 Pin Configuration and Functions
    1. 4.1 Pin Functions
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  6. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Voltage Regulator Assignment and Powergood Comparator Logic Assignment (External Voltage Regulator or Load Switch) for Skylake and Kabylake Platform
      2. 6.3.2  Generic Powergood Window Comparator with Open-Drain Output
      3. 6.3.3  Powergood Window Comparator
      4. 6.3.4  3.3-V LDO and 3V3SW Load Switch
      5. 6.3.5  5-V LDO and 5VSW Load Switch
      6. 6.3.6  RTC Selector and 3.1-V LDO
      7. 6.3.7  Power Path Comparators
      8. 6.3.8  UVLO Comparators
      9. 6.3.9  Temperature Comparator
      10. 6.3.10 Low Power Mode (LPM) / Connected Standby / Instant Go of VRs
      11. 6.3.11 Enable and Powergood of VRs
      12. 6.3.12 VR4 VDDQ and LDO1 VTT Enabling
      13. 6.3.13 Converters
        1. 6.3.13.1  Power Save Mode
        2. 6.3.13.2  Voltage Regulator Startup
        3. 6.3.13.3  Powergood, Power Fault, and Emergency Power Shutdown
        4. 6.3.13.4  Current Limit
        5. 6.3.13.5  Output Discharge Feature
        6. 6.3.13.6  Output Voltage Control
        7. 6.3.13.7  Converter Low Power Mode Operation
        8. 6.3.13.8  Controller Low Power Mode Operation
        9. 6.3.13.9  Controller Internal Ramp Comparator
        10. 6.3.13.10 Undervoltage Lockout
      14. 6.3.14 Coincell Selector
        1. 6.3.14.1 Functional Description of RTC Powerpath and LDO
    4. 6.4 Device Functional Modes
      1. 6.4.1  OFF State - No VIN and No Backup Battery
      2. 6.4.2  Startup
      3. 6.4.3  Ready State
      4. 6.4.4  S5/S4 State
      5. 6.4.5  S3 State
      6. 6.4.6  S0 State
      7. 6.4.7  Standby
      8. 6.4.8  DSx State
      9. 6.4.9  Emergency Shutdown
      10. 6.4.10 Backup Battery / G3 - No VIN
    5. 6.5 Programming
      1. 6.5.1 I2C - Interface
        1. 6.5.1.1 F/S-Mode Protocol
        2. 6.5.1.2 Diagrams of I2C Protocol
    6. 6.6 Register Map
      1. 6.6.1 Registers
        1. 6.6.1.1  VENDORID Register (address = 0x00) [reset = 00100010]
        2. 6.6.1.2  REVID Register (address = 0x01) [reset = 00000000]
        3. 6.6.1.3  IRQLVL1 Register (address = 0x02) [reset = 00000000]
        4. 6.6.1.4  PWRSRCINT Register (address = 0x04) [reset = 00000000]
        5. 6.6.1.5  PMUINT Register (address = 0x05) [reset = 00000000]
        6. 6.6.1.6  RESETIRQ1 Register (address = 0x08) [reset = 00000000]
        7. 6.6.1.7  RESETIRQ2 Register (address = 0x09) [reset = 00000000]
        8. 6.6.1.8  MPMUINT Register (address = 0x0B) [reset = 00010100]
        9. 6.6.1.9  MPWRSRCINT Register (address = 0x0C) [reset = 01111000]
        10. 6.6.1.10 RESETIRQ1MASK Register (address = 0x11) [reset = 00110000]
        11. 6.6.1.11 RESETIRQ2MASK Register (address = 0x12) [reset = 00000010]
        12. 6.6.1.12 IRQLVL1msK Register (address = 0x13) [reset = 10100101]
        13. 6.6.1.13 PBCONFIG Register (address = 0x14) [reset = 00011111]
        14. 6.6.1.14 PBSTATUS Register (address = 0x15) [reset = 00000000]
        15. 6.6.1.15 PWRSTAT1 Register (address = 0x16) [reset = 00000000]
        16. 6.6.1.16 PWRSTAT2 Register (address = 0x17) [reset = 00000000]
        17. 6.6.1.17 PGMASK1 Register (address = 0x18) [reset = 00000000]
        18. 6.6.1.18 PGMASK2 Register (address = 0x19) [reset = 00000000]
        19. 6.6.1.19 VCCIOCNT Register (address = 0x30) [reset = 00001010]
        20. 6.6.1.20 V5ADS3CNT Register (address = 0x31) [reset = 00101010]
        21. 6.6.1.21 V33ADSWCNT Register (address = 0x32) [reset = 00101010]
        22. 6.6.1.22 V33APCHCNT Register (address = 0x33) [reset = 00001010]
        23. 6.6.1.23 V18ACNT Register (address = 0x34) [reset = 00101010]
        24. 6.6.1.24 V18U25UCNT Register (address = 0x35) [reset = 00001010]
        25. 6.6.1.25 V1P2UCNT Register (address = 0x36) [reset = 00111010]
        26. 6.6.1.26 V100ACNT Register (address = 0x37) [reset = 00011010]
        27. 6.6.1.27 V085ACNT Register (address = 0x38) [reset = 00101010]
        28. 6.6.1.28 VRMODECTRL Register (address = 0x3B) [reset = 00111111]
        29. 6.6.1.29 DISCHCNT1 Register (address = 0x3C) [reset = 00000000]
        30. 6.6.1.30 DISCHCNT2 Register (address = 0x3D) [reset = 00000000]
        31. 6.6.1.31 DISCHCNT3 Register (address = 0x3E) [reset = 00000000]
        32. 6.6.1.32 DISCHCNT4 Register (address = 0x3F) [reset = 00000000]
        33. 6.6.1.33 PWRGDCNT1 Register (address = 0x40) [reset = 01011111 ]
        34. 6.6.1.34 VREN Register (address = 0x41) [reset = 00000000]
        35. 6.6.1.35 REGLOCK Register (address = 0x42) [reset = 00000000]
        36. 6.6.1.36 VRENPINMASK Register (address = 0x43) [reset = 00000000]
        37. 6.6.1.37 RSTCTRL Register (address = 0x48) [reset = 00011100]
        38. 6.6.1.38 SDWNCTRL Register (address = 0x49) [reset = 00000000]
        39. 6.6.1.39 VDLMTCRT Register (address = 0x51) [reset = 00000101]
        40. 6.6.1.40 ACOKDBDM Register (address = 0x69) [reset = 00001111]
        41. 6.6.1.41 LOWBATTDET Register (address = 0x6A) [reset = 11111000]
        42. 6.6.1.42 SPWRSRCINT Register (address = 0x6F) [reset = 00000000]
        43. 6.6.1.43 CLKCTRL1 Register (address = 0xD0) [reset = 00000000]
        44. 6.6.1.44 COMPA_REF Register (address = 0xDD) [reset = 00000000]
        45. 6.6.1.45 COMPB_REF Register (address = 0xDE) [reset = 00000000]
        46. 6.6.1.46 COMPC_REF Register (address = 0xDF) [reset = 00000000]
        47. 6.6.1.47 COMPD_REF Register (address = 0xE0) [reset = 00000000]
        48. 6.6.1.48 COMPE_REF Register (address = 0xE1) [reset = 00000000]
        49. 6.6.1.49 COMPF_REF Register (address = 0xE2) [reset = 00000000]
        50. 6.6.1.50 COMPG_REF Register (address = 0xE3) [reset = 00000000]
        51. 6.6.1.51 COMPH_REF Register (address = 0xE4) [reset = 00000000]
        52. 6.6.1.52 PWFAULT_MASK1 Register (address = 0xE5) [reset = 00000000]
        53. 6.6.1.53 PWFAULT_MASK2 Register (address = 0xE6) [reset = 00000000]
        54. 6.6.1.54 PGOOD_STAT1 Register (address = 0xE7) [reset = 00000000]
        55. 6.6.1.55 PGOOD_STAT2 Register (address = 0xE8) [reset = 00000000]
        56. 6.6.1.56 MISC_BITS Register (address = 0xE9) [reset = 00010000]
        57. 6.6.1.57 STDBY_CTRL Register (address = 0xEA) [reset = 11111110]
        58. 6.6.1.58 TEMPCRIT Register (address = 0xEB) [reset = 00000000]
        59. 6.6.1.59 TEMPHOT Register (address = 0xEC) [reset = 00000000]
        60. 6.6.1.60 VREN_PIN_OVR Register (address = 0xEE) [reset = 00000000]
  7. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Controller Design Procedure
          1. 7.2.2.1.1 Selecting the Inductor
          2. 7.2.2.1.2 Selecting the Output Capacitors
          3. 7.2.2.1.3 Selecting the FETs
          4. 7.2.2.1.4 Bootstrap Capacitor
          5. 7.2.2.1.5 Setting the Current Limits
          6. 7.2.2.1.6 Selecting the Input Capacitors
        2. 7.2.2.2 Converter Design Procedure
          1. 7.2.2.2.1 Selecting the Inductor
          2. 7.2.2.2.2 Selecting the Output Capacitors
          3. 7.2.2.2.3 Selecting the Input Capacitors
        3. 7.2.2.3 LDO Design Procedure
        4. 7.2.2.4 Board Temperature Monitoring Design Procedure
        5. 7.2.2.5 Power Path Design Procedure
      3. 7.2.3 Application Performance Curves
      4. 7.2.4 Specific Application - TPS650830 Powering the Intel SkyLake and Kabylake Platform Volume Configuration
        1. 7.2.4.1 Design Requirements
        2. 7.2.4.2 Detailed Design Procedure
          1. 7.2.4.2.1 Output Inductance and Capacitance
        3. 7.2.4.3 Application Performance Curves
    3. 7.3 System Example
    4. 7.4 Do's and Don'ts
  8. 8 Power Supply Recommendations
  9. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Fanout for ZAJ using Type 4 Routing
      2. 9.1.2 Fanout for ZCG using Type 3 Routing
      3. 9.1.3 Layout Checklist
    2. 9.2 Layout Example
      1. 9.2.1 Controller Layout
      2. 9.2.2 ZAJ Package
      3. 9.2.3 ZCG Package
    3. 9.3 Thermal Considerations
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Development Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Community Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

TPS650830 7x7Ballout.gif Figure 4-1 168-Pin 7x7 ZAJ NFBGA (Top View)
TPS650830 9x9Ballout.gif Figure 4-2 159-Pin 9x9 ZCG NFBGA (Top View)

4.1 Pin Functions

Table 4-1 Pin Functions

PIN I/O TYPE(1) DESCRIPTION
NAME ZAJ PACKAGE
NUMBER		 ZCG PACKAGE
NUMBER
ACIN E2 H3 I AS AC Adaptor voltage sense
ACOK D11 F13 I D ACOK input
ACSWONZ J2 M3 O D AC adaptor switch ON power-path (Open-drain output) (active low)
AGND F8, G8, H8, J8, F7, G7, H7, J7, K7, F6, G6, H6, J6, K6, G5, H5, J5 - - A Analog GND - tie directly to the ground plane
AGND1 C1 E1 - A Analog GND1 - tie directly to the ground plane
AGND2 K1 N1 - A Analog GND2 - tie directly to the ground plane
AGND3 L13 N16 - A Analog GND3 - tie directly to the ground plane
AGND4 D13 E16 - A Analog GND4 - tie directly to the ground plane
ALL_SYS_PWRGD G11 F15 O D Non-core rails powergood, All PMIC and specified monitored VRs power good (Open-drain output)
BAT1 F1 H1 I AS Battery 1 voltage sense input
BAT2 G1 J1 I AS Battery 2 voltage sense input
BAT1SWONZ F2 J2 O D Battery 1 switch ON power-path (Open-drain output) (active low)
BAT2SWONZ G2 K3 O D Battery 2 switch ON power-path (Open-drain output) (active low)
DDRID D4 C2 I D VR4 Output voltage selection. Low = 1.2 V, High = 1.35 V, Float = 1.1 V.
DDR_VTT_CTRL E3 E4 I D LDO1 Enable, and DVS control of VR4
DPWROK K12 M15 O D Delayed version of V3.3A_DSW_PG (Open-drain output)
DRVHVR1 N12 T14 O VR VR1 High side gate drive output (external power FET)
DRVHVR3 A12 A14 O VR VR3 High side gate drive output (external power FET)
DRVHVR4 A2 A3 O VR VR4 High side gate drive output (external power FET)
DRVHVR5 M1 T3 O VR VR5 High side gate drive output (external power FET)
DRVLVR1 N9 T11 O VR VR1 Low side gate drive output (external power FET)
DRVLVR3 A9 A11 O VR VR3 Low side gate drive output (external power FET)
DRVLVR4 A5 A6 O VR VR4 Low side gate drive output (external power FET)
DRVLVR5 N4 T6 O VR VR5 Low side gate drive output (external power FET)
DS3_VREN K13 M16 O D DS3 VR enable (enables external power switches) (Push-pull output)
ECVCC L1 P1 I AS EC VCC supply
EC_ONOFFZ K4 M5 O D Debounced version of PWRBTNIN (Open-drain output) (active low)
EC_RSTZ J3 L4 O D EC reset (Open-drain output) (active low)
ENA B12 B15 I D Enable for VSA powergood comparator
ENB C11 D13 I D Enable for VSB powergood comparator
ENC C12 D15 I D Enable for VSC powergood comparator
END J13 L16 I D Enable for VSD powergood comparator
ENE F10 J12 I D Enable for VSE powergood comparator
ENG B10 C14 I D Enable for VSG powergood comparator
ENF J12 L14 I D Enable for VSF powergood comparator
ENH L11 P13 I D Input to Level Shifter B general purpose level shifter.
ENLVA L6 P5 I D Enable level shifter A. Pin not used for TPS650830. Connect to ground if unused. (Level Shifter A input is ACOK pin)
ENVR1 M12 R15 I D VR1 Enable
ENVR2 F11 J14 I D VR2 Enable
ENVR3 E9 D11 I D VR3 Enable
ENVR4 C2 B2 I D VR4 Enable
ENVR5 M2 R2 I D VR5 Enable
EN3V3SW K3 L1 I D Enable for load switch from LDO3V pin to VOUT3V3SW output pin
EN5VSW M5 P7 I D Enable Internal load switch from 5-V switching regulator to LDO5V output through VIN5VSW. Connect to powergood of 5-V switching regulator.
FBLDO1 D8 F9 I AS LDO1 Feedback voltage kelvin sense, (Connect to vout of LDO1 at output load capacitor)
FBVR1N J9 K11 I AS VR1 Negative feedback remote sense (Connect to GND of VR1 at output load capacitor)
FBVR1P K10 J10 I AS VR1 Positive feedback remote sense (Connect to vout of VR1 at output load capacitor)
FBVR2N E10 G12 I AS VR2 Negative feedback remote sense (Connect to GND of VR2 at output load capacitor)
FBVR2P G10 G10 I AS VR2 Positive feedback remote sense (Connect to vout of VR2 at output load capacitor)
FBVR3N D7 E8 I AS VR3 Negative feedback remote sense (Connect to GND of VR3 at output load capacitor)
FBVR3P C10 F11 I AS VR3 Positive feedback remote sense (Connect to vout of VR3 at output load capacitor)
FBVR4N D5 E6 I AS VR4 Negative feedback remote sense (Connect to GND of VR4 at output load capacitor)
FBVR4P C3 F5 I AS VR4 Positive feedback remote sense (Connect to vout of VR4 at output load capacitor)
FBVR5N L4 H5 I AS VR5 Negative feedback remote sense (Connect to GND of VR5 at output load capacitor)
FBVR5P G4 J6 I AS VR5 Positive feedback remote sense (Connect to vout of VR5 at output load capacitor)
ILIMVR1 L9 M11 I AS VR1 Current limit setting, low-side FET valley current limit
ILIMVR3HS D10 E12 I AS VR3 Current limit setting, high-side FET peak current limit
ILIMVR3LS C9 E10 I AS VR3 Current limit setting, low-side FET valley current limit
ILIMVR4 D2 F3 I AS VR4 Current limit setting, low-side FET valley current limit
ILIMVR5HS K5 M7 I AS VR5 Current limit setting, high-side FET peak current limit
ILIMVR5LS L5 N6 I AS VR5 Current limit setting, low-side FET valley current limit
LDO3V N8 T10 O AS 3.3-V LDO used as a reference voltage, and as a pull-up supply.
LDO5V N7 T9 O AS 5-V internal supply used primarily for the gate drives
LVA L12 N14 O D Level shifter A open-drain output, used for BC_ACOK output level shifted to EC_VCC. Input is from ACOK pin
LVB L10 N12 O D Level shifter B push-pull output, level shifted to VDDLV. Input is from ENH pin
NVDC# H9 K9 I D NVDC select [two-level: Low = NVDC, High = non-NVDC]. Connect NVDC# to GND for NVDC, Connect NVDC# to LDO3V for non-NVDC
PCH_PWRBTNZ K2 N2 O D Power button signal to PCH (Open-drain output) (active low)
PCH_PWROK E11 G14 O D Core and Non Core powergood, Delayed version of ALL_SYS_PWRGD, (Open-drain output)
PGA D6 C12 O D Powergood comparator output, push-pull to VDDPG
PGB C5 A10 O D Powergood comparator output, push-pull to VDDPG
PGC C6 D7 O D Powergood comparator output, push-pull to VDDPG
PGD H3 J4 O D Powergood comparator output, push-pull to VDDPG
PGE C4 D5 O D Powergood comparator output, push-pull to VDDPG
PGF H4 K5 O D Powergood comparator output, push-pull to VDDPG
PGG F3 G4 O D Powergood comparator output, open-drain output
PGH M6 R8 O D Powergood comparator output, open-drain output
PGNDLDO1 A7, B7 A8, B8 - VR LDO1 Power GND
PGNDVR1 N10 T12 - VR VR1 Power GND
PGNDVR2 G12, G13 J15, J16 - VR VR2 Power GND
PGNDVR3 A10 A12 - VR VR3 Power GND
PGNDVR4 A4 A5 - VR VR4 Power GND
PGNDVR5 N3 T5 - VR VR5 Power GND
PGVR1 M9 P11 O D VR1 powergood comparator output (Push-pull output)
PGVR2 E12 H13 O D VR2 powergood comparator output (Push-pull output)
PGVR3 B9 B11 O D VR3 powergood comparator output (Push-pull output)
PGVR4 B5 C6 O D VR4 powergood comparator output (Open-drain output)
PGVR5 M4 R6 O D VR5 powergood comparator output (Push-pull output)
PMIC_INTZ D12 E14 O D PMIC to EC interrupt (Open-drain output) (active low)
PWRBTNIN H2 L2 I AS Power button input (internal pull-up to LDO3V) (active low)
RESETZ C8 D9 O D Global disable output for external converters/power tree (active low)
RSMRSTZ_PWRGD J11 F16 O D Resume Reset powergood (Open-drain output) (active low)
SCLK J1 M1 I D I2C Clock
SDA H1 K1 I/O D I2C Data
SHUTDOWNZ C7 C8 I D Set shutdown mode (all supplies off) (active low)
SLAVEADDR L3 N4 I D I2C Slave Address select (low = 0x30, high = 0x32, open = float = 0x34). Keep same connection during operation.
STANDBYZ D9 C10 I D Set rails in standby when low (low power mode)
SWVR1 N11 T13 I VR VR1 Switch node connection
SWVR2 H12, H13 K15, K16 I VR VR2 Switch node connection
SWVR3 A11 A13 I VR VR3 Switch node connection
SWVR4 A3 A4 I VR VR4 Switch node connection
SWVR5 N2 T4 I VR VR5 Switch node connection
SYS_PWROK H11 K13 O D Delayed version of ALL_SYS_PWRGD (Open-drain output)
TEMP_ALERTZ L2 P3 O D Open-drain output of silicon temperature sensor. Input to Power Monitor Unit (connect to PROCHOT# of system). Active low, recommended pull-up to V1.00S with 50 Ω.
TRIPZ H10 L12 O D VCOMP comparator push-pull output (active low)
VBATTBKUP B13 C16 I AS RTC backup battery supply connection
VBSTVR1 M11 R14 I VR VR1 Bootstrap pin
VBSTVR3 B11 B13 I VR VR3 Bootstrap pin
VBSTVR4 B3 C4 I VR VR4 Bootstrap pin
VBSTVR5 M3 R4 I VR VR5 Bootstrap pin
VCCST_PWRGD E4 C1 O D VCCST powergood (Open-drain output)
VCOMP J4 L6 I AS VCOMP comparator input
VDCSNS G3 G1 I AS VDC voltage monitor
VDDIO E1, M13 F1, P16 I VR Voltage supply input for I/O buffers. VDDIO should be tied to LDO3V (3.3 V)
VDDLV L8 N10 I VR LVx buffer supply, sets output level for Level Shifter pins
VDDPG D1 G2 I VR PGx supply, sets output level for PG pins for A-H, if PG pin is push-pull
VDD5 VPROGOTP D3 D3 I AS Always connect to LDO5V. supply voltage for OTP programming (must be connected to LDO5V in normal operation)
VIN N6 T8 I VR IC input voltage
VINLDO1 A6, B6 A7, B7 I VR LDO1 Input supply
VINLDO3 M8 R10 I VR LDO3V input supply
VINLDO1S F9 H9 I AS LDO1 Input voltage reference sense (Connect to vout of VR4 at output load capacitor)
VINPP E5 H7 I AS VIN for Power Path Domain. Connect to external diode OR from: AC, BAT1, BAT2.
VINVR2 F12, F13 H15, H16 I VR VR2 Power Input voltage. Connect to a 3.3-V voltage regulator, such as V3.3A_DSW .
VINVR3 G9 H11 I AS VR3 Input voltage sense and high-side current-sense (Kelvin connect to drain of high-side FET)
VINVR5 L7 N8 I AS VR5 Input voltage sense and high-side current-sense (Kelvin connect to drain of high-side FET)
VIN5VSW N5 T7 I VR Internal load switch from 5-V switching regulator to LDO5Voutput. Connect VIN5VSW to 5-V switching regulator output.
VOUTLDO1 A8, B8 A9, B9 O VR LDO1 Output voltage, VOUTLDO1 = (1/2 * VINLDO1SNS)
VOUT3V3SW M7 P9 O VR EC domain load switch output and discharge path from LDO3V
VREF1V25 B1 D1 O AS Decoupling cap connection for internal voltage reference
VREGVR1 M10 R12 I VR 5-V drive supply input (shorted on board with LDO5V), supply for VR1 and VR5
VREGVR2 E13 G16 I VR VR2 5-V drive supply input (shorted on board with LDO5V)
VREGVR4 B4 B5 I VR VR4 5-V drive supply input (shorted on board with LDO5V), shared with VR3
VSA E7 F7 I AS Powergood comparator input and discharge path for external rail
VSB K9 M9 I AS Powergood comparator input and discharge path for external rail
VSC K8 L8 I AS Powergood comparator input and discharge path for external rail
VSD E6 L10 I AS Powergood comparator input and discharge path for external rail
VSE F4 G6 I AS Powergood comparator input and discharge path for external rail
VSF E8 J8 I AS Powergood comparator input and discharge path for external rail
VSG J10 K7 I AS Powergood comparator input and discharge path for external rail
VSH F5 G8 I AS Powergood comparator input and discharge path for external rail
V3P3A_RTC C13 D16 O AS PCH RTC power supply
1HZ K11 M13 O D 1-Hz clock output for waking up embedded controller, EC.
DEPOPULATED BALL - FOR VIAS No Depopulated Balls for Vias in 7x7. Type 4 PC put micro-vias under each ball pad B3, B4, B6, B10, B12, B14, C3, C5, C7, C9, C11, C13, C15, D2, D4, D6, D8, D10, D12, D14, E2, E3, E5, E7, E9, E11, E13, E15, F2, F4, F6, F8, F10, F12, F14, G3, G5, G7, G9, G11, G13, G15, H2, H4, H6, H8, H10, H12, H14, J3, J5, J7, J9, J11, J13, K2, K4, K6, K8, K10, K12, K14, L3, L5, L7, L9, L11, L13, L15, M2, M4, M6, M8, M10, M12, M14, N3, N5, N7, N9, N11, N13, N15, P2, P4, P6, P8, P10, P12, P14, P15, R3, R5, R7, R9, R11, R13, DEPOPULATED BALL - VIA PLACEMENT FOR INTERNAL BALL ROUTES - For Type3 PCBs, put a plated through-hole (PTH) via at each depopulated ball, to connect to the internal row balls.
DEPOPULATED BALL - PICK-N-PLACE INDICATOR B2 C3 (also used for via - see below) DEPOPULATED BALL - PICK-N-PLACE INDICATOR
NC POPULATED BALL - CORNERS A1, A13, N1, N13 A1, A2, B1, A15, A16, B16, R16, T16, T15, R1, T1, T2 POPULATED BALL - CORNERS - solder to PCB for mechanical strength
(1) VR – VR Critical, AS – Analog Sensitive, D – Digital, A - AGND