SWCS134 October   2017 TPS6508700

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Pin Configuration and Functions
    1. 3.1 Pin Functions
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  Electrical Characteristics: Total Current Consumption
    6. 4.6  Electrical Characteristics: Reference and Monitoring System
    7. 4.7  Electrical Characteristics: Buck Controllers
    8. 4.8  Electrical Characteristics: Synchronous Buck Converters
    9. 4.9  Electrical Characteristics: LDOs
    10. 4.10 Electrical Characteristics: Load Switches
    11. 4.11 Digital Signals: I2C Interface
    12. 4.12 Digital Input Signals (CTLx)
    13. 4.13 Digital Output Signals (IRQB, GPOx)
    14. 4.14 Timing Requirements
    15. 4.15 Switching Characteristics
    16. 4.16 Typical Characteristics
  5. 5Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 SMPS Voltage Regulators
      1. 5.3.1 Controller Overview
      2. 5.3.2 Converter Overview
      3. 5.3.3 Dynamic Voltage Scaling
      4. 5.3.4 Current Limit
    4. 5.4 LDO Regulators and Load Switches
      1. 5.4.1 VTT LDO
      2. 5.4.2 LDOA1-LDOA3
      3. 5.4.3 Load Switches
    5. 5.5 Power Good Information (PGOOD or PG) and GPO Pins
    6. 5.6 Power Sequencing and Voltage-Rail Control
      1. 5.6.1 Power-Up and Power-Down Sequencing
      2. 5.6.2 Emergency Shutdown
    7. 5.7 Device Functional Modes
      1. 5.7.1 Off Mode
      2. 5.7.2 Standby Mode
      3. 5.7.3 Active Mode
    8. 5.8 I2C Interface
      1. 5.8.1 F/S-Mode Protocol
    9. 5.9 Register Maps
      1. 5.9.1  Register Map Summary
      2. 5.9.2  DEVICEID: PMIC Device and Revision ID Register (offset = 1h) [reset = 10h]
      3. 5.9.3  IRQ: PMIC Interrupt Register (offset = 2h) [reset = 0h]
      4. 5.9.4  IRQ_MASK: PMIC Interrupt Mask Register (offset = 3h) [reset = FFh]
      5. 5.9.5  PMICSTAT: PMIC Status Register (offset = 4h) [reset = 0h]
      6. 5.9.6  SHUTDNSRC: PMIC Shut-Down Event Register (offset = 5h) [reset = 0h]
      7. 5.9.7  BUCK2CTRL: BUCK2 Control Register (offset = 21h) [reset = 50h]
      8. 5.9.8  BUCK3DECAY: BUCK3 Decay Control Register (offset = 22h) [reset = 70h]
      9. 5.9.9  BUCK3VID: BUCK3 VID Register (offset = 23h) [reset = 70h]
      10. 5.9.10 BUCK3SLPCTRL: BUCK3 Sleep Control VID Register (offset = 24h) [reset = 70h]
      11. 5.9.11 BUCK4CTRL: BUCK4 Control Register (offset = 25h) [reset = Dh]
      12. 5.9.12 BUCK5CTRL: BUCK5 Control Register (offset = 26h) [reset = Dh]
      13. 5.9.13 BUCK6CTRL: BUCK6 Control Register (offset = 27h) [reset = Dh]
      14. 5.9.14 LDOA2CTRL: LDOA2 Control Register (offset = 28h) [reset = Ch]
      15. 5.9.15 LDOA3CTRL: LDOA3 Control Register (offset = 29h) [reset = 3Ch]
      16. 5.9.16 DISCHCTRL1: Discharge Control1 Register (offset = 40h) [reset = 55h]
      17. 5.9.17 DISCHCTRL2: Discharge Control2 Register (offset = 41h) [reset = 55h]
      18. 5.9.18 DISCHCTRL3: Discharge Control3 Register (offset = 42h) [reset = 15h]
      19. 5.9.19 PG_DELAY1: Power Good Delay1 Register (offset = 43h) [reset = 0h]
      20. 5.9.20 FORCESHUTDN: Force Emergency Shutdown Control Register (offset = 91h) [reset = 0h]
      21. 5.9.21 BUCK2SLPCTRL: BUCK2 Sleep Control Register (offset = 93h) [reset = 50h]
      22. 5.9.22 BUCK4VID: BUCK4 VID Register (offset = 94h) [reset = 20h]
      23. 5.9.23 BUCK4SLPVID: BUCK4 Sleep VID Register (offset = 95h) [reset = 20h]
      24. 5.9.24 BUCK5VID: BUCK5 VID Register (offset = 96h) [reset = 70h]
      25. 5.9.25 BUCK5SLPVID: BUCK5 Sleep VID Register (offset = 97h) [reset = E8h]
      26. 5.9.26 BUCK6VID: BUCK6 VID Register (offset = 98h) [reset = E8h]
      27. 5.9.27 BUCK6SLPVID: BUCK6 Sleep VID Register (offset = 99h) [reset = E8h]
      28. 5.9.28 LDOA2VID: LDOA2 VID Register (offset = 9Ah) [reset = FFh]
      29. 5.9.29 LDOA3VID: LDOA3 VID Register (offset = 9Bh) [reset = AAh]
      30. 5.9.30 BUCK123CTRL: BUCK1-3 Control Register (offset = 9Ch) [reset = 7h]
      31. 5.9.31 PG_DELAY2: Power Good Delay2 Register (offset = 9Dh) [reset = 21h]
      32. 5.9.32 SWVTT_DIS: SWVTT Disable Register (offset = 9Fh) [reset = 0h]
      33. 5.9.33 I2C_RAIL_EN1: VR Pin Enable Override1 Register (offset = A0h) [reset = 80h]
      34. 5.9.34 I2C_RAIL_EN2/GPOCTRL: VR Pin Enable Override2/GPO Control Register (offset = A1h) [reset = 89h]
      35. 5.9.35 PWR_FAULT_MASK1: VR Power Fault Mask1 Register (offset = A2h) [reset = C0h]
      36. 5.9.36 PWR_FAULT_MASK2: VR Power Fault Mask2 Register (offset = A3h) [reset = 3Fh]
      37. 5.9.37 GPO1PG_CTRL1: GPO1 PG Control1 Register (offset = A4h) [reset = C2h]
      38. 5.9.38 GPO1PG_CTRL2: GPO1 PG Control2 Register (offset = A5h) [reset = AFh]
      39. 5.9.39 GPO4PG_CTRL1: GPO4 PG Control1 Register (offset = A6h) [reset = 0h]
      40. 5.9.40 GPO4PG_CTRL2: GPO4 PG Control2 Register (offset = A7h) [reset = 0h]
      41. 5.9.41 GPO2PG_CTRL1: GPO2 PG Control1 Register (offset = A8h) [reset = C0h]
      42. 5.9.42 GPO2PG_CTRL2: GPO2 PG Control2 Register (offset = A9h) [reset = 2Fh]
      43. 5.9.43 GPO3PG_CTRL1: GPO3 PG Control1 Register (offset = AAh) [reset = 0h]
      44. 5.9.44 GPO3PG_CTRL2: GPO3 PG Control2 Register (offset = ABh) [reset = 0h]
      45. 5.9.45 MISCSYSPG Register (offset = ACh) [reset = FFh]
      46. 5.9.46 LDOA1CTRL: LDOA1 Control Register (offset = AEh) [reset = 7Dh]
      47. 5.9.47 PG_STATUS1: Power Good Status1 Register (offset = B0h) [reset = 0h]
      48. 5.9.48 PG_STATUS2: Power Good Status2 Register (offset = B1h) [reset = 0h]
      49. 5.9.49 PWR_FAULT_STATUS1: Power Fault Status1 Register (offset = B2h) [reset = 0h]
      50. 5.9.50 PWR_FAULT_STATUS2: Power Fault Status2 Register (offset = B3h) [reset = 0h]
      51. 5.9.51 TEMPCRIT: Temperature Fault Status Register (offset = B4h) [reset = 0h]
      52. 5.9.52 TEMPHOT: Temperature Hot Status Register (offset = B5h) [reset = 0h]
      53. 5.9.53 OC_STATUS: Overcurrent Fault Status Register (offset = B6h) [reset = 0h]
  6. 6Applications, Implementation, and Layout
    1. 6.1 Application Information
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
        1. 6.2.2.1 Controller Design Procedure
          1. 6.2.2.1.1 Controller With External Feedback Resistor
          2. 6.2.2.1.2 Selecting the Inductor
          3. 6.2.2.1.3 Selecting the Output Capacitors
          4. 6.2.2.1.4 Selecting the FETs
          5. 6.2.2.1.5 Bootstrap Capacitor
          6. 6.2.2.1.6 Setting the Current Limit
          7. 6.2.2.1.7 Selecting the Input Capacitors
        2. 6.2.2.2 Converter Design Procedure
          1. 6.2.2.2.1 Selecting the Inductor
          2. 6.2.2.2.2 Selecting the Output Capacitors
          3. 6.2.2.2.3 Selecting the Input Capacitors
        3. 6.2.2.3 LDO Design Procedure
      3. 6.2.3 Application Curves
      4. 6.2.4 Layout
        1. 6.2.4.1 Layout Guidelines
        2. 6.2.4.2 Layout Example
    3. 6.3 Power Supply Coupling and Bulk Capacitors
    4. 6.4 Do's and Don'ts
  7. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Third-Party Products Disclaimer
    2. 7.2 Documentation Support
      1. 7.2.1 Related Documentation
    3. 7.3 Receiving Notification of Documentation Updates
    4. 7.4 Community Resources
    5. 7.5 Trademarks
    6. 7.6 Electrostatic Discharge Caution
    7. 7.7 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RSK|64
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Applications, Implementation, and Layout

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

6.1 Application Information

The TPS6508700 device can be used in several different applications from computing, industrial interfacing and much more. Section 6.2 describes the general application information and provides a more detailed description on the TPS6508700 device that powers the AMD system. Figure 6-2 shows the functional block diagram for the device, which outlines the typical external connections required for proper device functionality.

6.2 Typical Application

TPS6508700 8700_CTL_Implementation.gif Figure 6-1 CTL Pin Implementation Option
TPS6508700 8700_Application_BlockDiagram.gif Figure 6-2 Typical Application Example

6.2.1 Design Requirements

The TPS6508700 device requires decoupling capacitors on the supply pins. Follow the values for recommended capacitance on these supplies given in Section 4. The controllers, converter, LDOs, and some other features can be adjusted to meet specific application needs. Section 6.2.2 describes how to design and adjust the external components to achieve the desired performance. In most cases, the controller and converter designs should be copied directly from the AMD reference design. If significant changes must be made, some guidelines are provided in Section 6.2.2.

6.2.2 Detailed Design Procedure

6.2.2.1 Controller Design Procedure

Designing the controller can be broken down into the following steps:

  1. Design the output filter
  2. Select the FETs
  3. Select the bootstrap capacitor
  4. Select the input capacitors
  5. Set the current limits

The BUCK1, BUCK2, and BUCK6 controllers require a 5-V supply and capacitors at their corresponding DRV5V_x_x pins. For most applications, the DRV5V_x_x input must come from the LDO5P0 pin to ensure uninterrupted supply voltage. A 2.2-µF, X5R, 20%, 10-V, or similar capacitor must be used for decoupling.

TPS6508700 App_Controller.gif Figure 6-3 Controller Diagram

6.2.2.1.1 Controller With External Feedback Resistor

For BUCK1, the voltage can be set using external feedback resistor. For all other bucks, the voltage is set by the default OTP settings and no resistor divider is required. For BUCK1, The internal voltage reference is set to 0.4 V.The output voltage is set with a resistor divider from the output node to the FB pin. TI recommends using a 1% tolerance or better to get accurate number. Use Equation 1 to calculate the value of R2.

Equation 1. R2 = R1 (0.4 / VO – 0.4)

To set the output voltage to 5 V, use a value of 294 kΩ for R1 and 25.5 kΩ for R2.

TPS6508700 tps6508700-controller-diagram-with-external-feedback-resistor.gif Figure 6-4 Controller Diagram With External Feedback Resistor

6.2.2.1.2 Selecting the Inductor

Placement of an inductor is required between the external FETs and the output capacitors. Together, the inductor and output capacitors make the double-pole that contributes to stability. Additionally, the inductor is directly responsible for the output ripple, efficiency, and transient performance. As the inductance used increases, the ripple current decreases, which typically results in increased efficiency. However, as the inductance used increases, the transient performance decreases. Finally, the inductor selected must be rated for appropriate saturation current, core losses, and DC resistance (DCR).

Use Equation 2 to calculate the recommended inductance for the controller.

Equation 2. TPS6508700 App_InductorEquation.gif

where

  • VOUT is the typical output voltage.
  • VIN is the typical input voltage.
  • fSW is the typical switching frequency.
  • IOUT(MAX) is the maximum load current.
  • KIND is the ratio of ILripple to the IOUT(MAX). For this application, TI recommends that KIND is set to a value from 0.2 to 0.4.

With the chosen inductance value, the peak current for the inductor in steady state operation, IL(MAX), can be calculated using Equation 3. The rated saturation current of the inductor must be higher than the IL(MAX) current.

Equation 3. TPS6508700 App_ILMAXControllerEquation.gif

6.2.2.1.3 Selecting the Output Capacitors

TI recommends using ceramic capacitors with low ESR values to provide the lowest output voltage ripple. The output capacitor requires an X7R or an X5R dielectric. Y5V and Z5U dielectric capacitors, aside from their wide variation in capacitance over temperature, become resistive at high frequencies.

At light load currents, the controller operates in PFM mode, and the output voltage ripple is dependent on the output-capacitor value and the PFM peak inductor current. Higher output-capacitor values minimize the voltage ripple in PFM mode. To achieve the specified regulation performance and low output-voltage ripple, the DC-bias characteristic of ceramic capacitors must be considered. The effective capacitance of ceramic capacitors drops with increasing DC bias voltage.

TI recommends using small ceramic capacitors placed between the inductor and load with many vias to the power ground (PGND) plane for the output capacitors of the buck controllers. This solution typically provides the smallest and lowest cost solution available for D-CAP2 controllers.

The selection of the output capacitor is typically driven by the output transient response. Equation 4 provides a rough estimate of the minimum required capacitance to ensure proper transient response. Because the transient response is significantly affected by the board layout, some experimentation is expected to confirm that values derived in this section are applicable to any particular use case. Equation 4 is not meant to be an absolute requirement, but rather a rough starting point. Alternatively, some known combination values from which to begin are provided in Table 6-1.

Equation 4. TPS6508700 controller-CoutTrans.gif

where

  • ITRAN(MAX) is the maximum load current step.
  • L is the chosen inductance.
  • VOUT is the minimum programmed output voltage.
  • VIN is the maximum input voltage.
  • VUNDER is the minimum allowable undershoot from the programmable voltage.

In cases where the transient current change is very low, the DC stability may become important. Use Equation 5 to calculate the approximate amount of capacitance required to maintain DC stability. Again, this equation is provided as a starting point; actual values will vary on a board-to-board case.

Equation 5. TPS6508700 App_OutputCapStability.gif

where

  • VOUT is the maximum programmed output voltage
  • 50 µs is based on internal ramp setup
  • VIN is the minimum input voltage
  • fSW is the typical switching frequency
  • L is the chosen inductance

The maximum valuable between Equation 4 and Equation 5 must be selected. Table 6-1 lists some known inductor-capacitor combinations.

Table 6-1 Known LC Combinations

ITRAN(max) (A) L (µH) VOUT (V) VUNDER (V) COUT(µF)
3.5 0.47 1 0.05 110
4 0.47 1 0.05 220
5 0.47 1.35 0.068 220
8 0.33 1 0.06 440
20 0.22 1 0.16 550

6.2.2.1.4 Selecting the FETs

This controller is designed to drive two NMOS FETs. Typically, lower RDSON values are better for improving the overall efficiency of the controller; however, higher gate-charge thresholds result in lower efficiency so the twovalues must be balanced for optimal performance. As the RDSON for the low-side FET decreases, the minimum current limit increases; therefore, appropriately select the values for the FETs, inductor, output capacitors, and current limit resistor. TI's CSD87331Q3D, CSD87381P, and CSD87588N devices are recommended for the controllers, depending on the required maximum current.

6.2.2.1.5 Bootstrap Capacitor

To ensure the internal high-side gate drivers are supplied with a stable low-noise supply voltage, a capacitor must be connected between the SWx pins and the respective BOOTx pins. TI recommends placing ceramic capacitors with a value of 0.1 µF for the controllers. During testing, a 0.1-µF, size 0402, 10-V capacitor is used for the controllers.

TI recommends reserving a small resistor in series with the bootstrap capacitor in case the turnon and turnoff of the FETs must be slowed to reduce voltage ringing on the switch node, which is a common practice for controller design.

6.2.2.1.6 Setting the Current Limit

The current-limiting resistor value must be chosen based on Equation 1.

6.2.2.1.7 Selecting the Input Capacitors

Because of the nature of the switching controller with a pulsating input current, a low-ESR input capacitor is required for best input-voltage filtering and also for minimizing the interference with other circuits caused by high input-voltage spikes. For the controller, a typical 2.2-µF capacitor can be used for the DRV5V_x_x pin to support the transients on the driver. For the FET input, 10 µF of input capacitance (after derating) is recommended for most applications. To achieve the low-ESR requirement, a ceramic capacitor is recommended. However, the voltage rating and DC-bias characteristic of ceramic capacitors must be considered. For better input-voltage filtering, the input capacitor can be increased without any limit.

NOTE

Use the correct capacitance value for the ceramic capacitor after derating to achieve the recommended input capacitance.

TI recommends placing a ceramic capacitor as close as possible to the FET across the respective VSYS and PGND pins of the FETs. The preferred capacitors for the controllers are two Murata GRM21BR61E226ME44: 22-µF, 0805, 25-V, ±20%, or similar capacitors.

6.2.2.2 Converter Design Procedure

Designing the converter has only two steps: design the output filter and select the input capacitors.

The converter must be supplied by a 5-V source. Figure 6-5 shows a diagram of the converter.

TPS6508700 App_Converter.gif Figure 6-5 Converter Diagram

6.2.2.2.1 Selecting the Inductor

Placement of an inductor between the external FETs and the output capacitors is required. Together, the inductor and output capacitors form a double pole in the control loop that contributes to stability. Additionally, the inductor is directly responsible for the output ripple, efficiency, and transient performance. As the inductance used increases, the ripple current decreases, which typically results in an increase in efficiency. However, with an increase in inductance used, the transient performance decreases. Finally, the inductor selected must be rated for appropriate saturation current, core losses, and DCR.

NOTE

Internal parameters for the converters are optimized for a 0.47-µH inductor for BUCK3 and a 1-µH inductor for BUCK4 and BUCK5; however, using other inductor values is possible as long as they are chosen carefully and thoroughly tested.
Equation 6. TPS6508700 App_InductorEquation.gif

With the chosen inductance value and the peak current for the inductor in steady state operation, IL(MAX) can be calculated using Equation 7. The rated saturation current of the inductor must be higher than the IL(MAX) current.

Equation 7. TPS6508700 App_ILMAXControllerEquation.gif

6.2.2.2.2 Selecting the Output Capacitors

Ceramic capacitors with low ESR values are recommended because they provide the lowest output voltage ripple. The output capacitor requires either an X7R or X5R rating. Y5V and Z5U capacitors, aside from the wide variation in capacitance over temperature, become resistive at high frequencies.

At light load currents, the converter operates in PFM mode and the output voltage ripple is dependent on the output-capacitor value and the PFM peak inductor current. Higher output-capacitor values minimize the voltage ripple in PFM mode. To achieve the specified regulation performance and low output-voltage ripple, the DC-bias characteristic of ceramic capacitors must be considered. The effective capacitance of ceramic capacitors drops with increasing DC-bias voltage.

For the output capacitors of the buck converters, TI recommends placing small ceramic capacitors between the inductor and load with many vias to the PGND plane. This solution typically provides the smallest and lowest-cost solution available for D-CAP2 controllers.

The output capacitance must equal or exceed the minimum capacitance listed for BUCK3, BUCK4, and BUCK5 (assuming quality layout techniques are followed).

6.2.2.2.3 Selecting the Input Capacitors

Because of the nature of the switching converter with a pulsating input current, a low-ESR input capacitor is required for the best input-voltage filtering and for minimizing the interference with other circuits caused by high input-voltage spikes. For the PVINx pin, 2.5 µF of input capacitance (after derating) is required for most applications. A ceramic capacitor is recommended to achieve the low-ESR requirement. However, the voltage rating and DC-bias characteristic of ceramic capacitors must be considered. The input capacitor can be increased without any limit for better input-voltage filtering.

NOTE

Use the correct capacitance value for the ceramic capacitor after derating to achieve the recommended input capacitance.

The preferred capacitor for the converters is one Samsung CL05A106MP5NUNC: 10-µF, 0402, 10-V, ±20%, or similar capacitor.

6.2.2.3 LDO Design Procedure

The VTT LDO must support the fast load transients from the DDR memory for termination. Therefore, TI recommends using ceramic capacitors to maintain a high amount of capacitance with low ESR on the VTT LDO outputs and inputs. The preferred output capacitors for the VTT LDO are the GRM188R60J226MEA0 from Murata (22 µF, 0603, 6.3 V, ±20%, or similar capacitors). The preferred input capacitor for the VTT LDO is the CL05A106MP5NUNC from Samsung (10-µF, 0402, 10-V, ±20%, or similar capacitor).

The remaining LDOs must have input and output capacitors chosen based on the values in Section 4.9.

6.2.3 Application Curves

TPS6508700 AC_01_swcs129.gif
Figure 6-6 BUCK2 Load Transient
TPS6508700 AC_02_swcs129.gif
Figure 6-7 BUCK2 Load Transient

6.2.4 Layout

6.2.4.1 Layout Guidelines

For all switching power supplies, the layout is an important step in the design, especially at high peak currents and high switching frequencies. If the layout is not carefully done, the regulator can have stability problems and EMI issues. Therefore, use wide and short traces for the main current path and for the power ground (PGND) tracks. The input capacitors, output capacitors, and inductors must be placed as close as possible to the device. Use a common-ground node for the power ground and use a different, isolated node for the control ground to minimize the effects of ground noise. Connect these ground nodes close to the AGND pin by one or two vias. Use of the design guide is highly recommended in addition to following these other basic requirements:

  • Do not allow the AGND, PGNDSNSx, or FBGND2 pin to connect to the thermal pad on the top layer.
  • To ensure proper sensing based on the FET RDSON, the PGNDSNSx pin must not connect to the board ground or to the PGND pin of the FET.
  • All inductors, input and output capacitors, and FETs for the converters and controller must be on the same board layer as the device.
  • To achieve the best regulation performance, place feedback connection points near the output capacitors and minimize the control feedback loop as much as possible.
  • Bootstrap capacitors must be placed close to the device.
  • The internal reference regulators must have their input and output capacitors placed close to the device pins.
  • Route the DRVHx and SWx pins as a differential pair. Ensure that a power-ground path is routed in parallel with the DRVLx pin, which provides optimal driver loops.

6.2.4.2 Layout Example

TPS6508700 App_LayoutOverall.gif Figure 6-8 EVM Layout Example With All Components on the Top Layer

6.3 Power Supply Coupling and Bulk Capacitors

This device is designed to work with several different input voltages. The minimum voltage on the VSYS pin is 5.6 V for the device to start up; however, this is a low power rail. The input to the FETs must be from 4.5 V to 21 V as long as the proper bill of materials (BOM) choices are made. The input to the converters must be 5 V. For the device to output maximum power, the input power must be sufficient. For the controllers, VIN must be able to supply sufficient input current for the output power of the application. For the converters, the PVINx converter must be able to supply 2 A (typical).

As a best practice, determine the power usage by the system and back-calculate the necessary power input based on the expected efficiency values.

6.4 Do's and Don'ts

  • Connect the LDO5V output to the DRV5V_x_x inputs. This output initially supplies 5 V for the drivers from the VSYS pin and then switches to using the 5-V buck converter when available for optimal efficiency.
  • Ensure that none of the control pins are potentially floating.
  • Include 0-Ω resistors on the DRVH or BOOT pins of the controllers on prototype boards, which allows for slowing the controllers if the system is unable to handle the noise generated by the large switching or if switching voltage is too large because of layout.
  • Do not connect the V5ANA power input to a different source other than PVINx. A mismatch here causes reference circuits to regulate incorrectly.
  • Do not supply the V5ANA power input before the VSYS. Reference biasing of the internal FETs may turn on the HS FET passing the input to the output until VSYS is biased.