7.3.1 Always On LDOs

As soon as a valid voltage at VSYS is applied, the LDOs start operating and providing a regulated output voltage at each of them. If DCDC1 is started, the output of the DCDC1 converter will be connected to the output of LDO1 with an internal bypass switch to ensure seamless transition. Finally, LDO1 will stop operating. LDO1 will restart when the voltage at its output drops below its regulation voltage. In this case, both outputs will be disconnected from each other. There will be no current flowing backward from the LDO1 output to the DCDC1 output. The same function is implemented for DCDC2 and LDO2.

7.3.2 Power Path Control

The device automatically switches adapter or battery power to the system load. The battery is connected to the system by default during power up or if the adapter power is not available. As soon as a valid voltage is detected on VACS and the voltage at VAC is higher than the battery voltage, the battery is disconnected and the AC power path switches controlled through the pins ACG and ACS are turned on. The system is powered through the adapter input. If the voltage on VACS is higher than the overvoltage protection threshold the AC power path switches are turned off or not turned on to protect the system from damage. Any voltage on VACS lower than the input undervoltage lockout (UVLO) threshold voltage will cause the AC power path switches to be off.

To protect the device and the system against reverse voltage additional external components are required to protect the pins VAC, VACS ACG and ACS which would be exposed to the reverse voltage. See the EVM documentation SLVU778 for more details.

In case the maximum adapter output current is not high enough to supply the complete system, the system can be powered through the adapter and the battery at the same time. If the adapter current is limited, the adapter voltage will drop to the battery voltage level and the backgate diode of the battery switch will conduct current.

To minimize the losses in this mode of operation, the battery switch is turned on. To detect whether there is still a power source connected at the AC input, the AC power path switches are turned off every 0.5 s for a few milliseconds. While the AC power path switches are off, VAC is discharged through a 1-kΩ resistor to GND. If the voltage at VACS did not drop below the input UVLO threshold voltage, the AC power path switches are turned on again to allow the power source connected to the AC input to supply the system again.

7.3.3 Supply Status Outputs

The status of the power supply is indicated through the status pins VACG, VBATG and VSYSG. All pins are open-drain outputs and need a pullup resistor to the respective logic supply voltage they are connected to.

VACG will be high if a voltage is detected at VAC and VACS which is in a useable window. This means the voltage detected at VACS must be lower than the overvoltage threshold and it must be higher than the input UVLO threshold voltage. Also, the voltage at VAC must be higher than battery voltage. If no battery is connected, the minimum voltage is above the UVLO threshold.

VSYSG will be high as soon as the system voltage, detected at VSYS_L1 and VSYS_L2, is above its undervoltage thresholds.

VBATG will be high if the voltage detected at FBC is between the minimum and the maximum voltage for battery good detection and the differential voltage V_SRN - V_VBAT is lower than 20 mV. This indicates that the battery discharge current is not exceeding the programmed maximum level.

7.3.4 Charger

Charging can be enabled by using the ENC pin or by programming the respective register through I²C. The charger will then start working when VACG is detected. If the battery is completely charged or charging has been terminated for any other reason, the charger will stay idle. Charging can be restarted by disabling the charger and enabling it again.

As soon as the charger is enabled it starts with battery detection as shown in Figure 36. If no battery or a battery short is detected the charger will continue with battery detection. If the battery is detected it will start charging.

Figure 36. Battery Detection

The charger controls a low constant-charge current during a precharge phase when the battery is at a very low voltage and must be recovered. The charger controls a high fast-charge current if the battery voltage is greater than the low voltage threshold and less than the charge termination voltage. If the battery voltage has reached the charge termination voltage, the charger controls this voltage until the charge current has decayed below the charge termination threshold or the fast-charge safety timer has timed out. Precharge current and charge termination current are either 10% of the programmed fast-charge current if the fast-charge current is set to 1 A or higher. Otherwise they will be controlled to 100 mA. A complete charging cycle is shown in Figure 37.

Figure 37. Charging Cycle

To support charging with weak power sources, the charger stays in operation even if it cannot control the charge current at the programmed level. For this operating condition, the charge termination based on low charge current can be turned off by programming the respective register.

The fast-charge safety timer is programmed to its lowest value by default. The time-out time can be increased by programming higher values in the respective registers. It cannot be turned off.

All charge currents are defined depending on the current sense resistor connected between the pins SRN and SRP. The maximum fast-charge current generates a 40 mV voltage drop across this resistor. All other currents are lower.

The charge termination voltage is defined by a resistive voltage divider connected between battery, feedback input of the charger (FBC), and GND. The maximum voltage at FBC which is controlled is typically 2.1 V.

The charger has also inputs to measure the battery cell temperature. It supports using two different temperature sensors which can be placed at different locations in the battery pack. For more details on the temperature sensing circuit, refer to Application and Implementation. For biasing the temperature sense resistor networks and the internal comparator reference the voltage at the VREFT pin is used. It is turned off if the charger is disabled.

Charge current and charge termination voltage can be programmed to lower than the maximum values using the digital interface. They are also controlled and forced to lower values depending on the measured battery cell temperature. The respective values for the five different temperature regions can be programmed in the charge control registers (CG_CTRLx) using the digital interface. Default settings for temperature thresholds and the respective fast-charge current and charge termination voltages are defined according to JEITA recommendations for multicell battery packs. The definitions for the thresholds and temperature zones are shown in Figure 38. Figure 38 also shows the default values for temperature thresholds, charge current and charge termination voltage, which are programmed in TPS65090A. The optional values which can be programmed through the digital interface, can be found in Electrical Characteristics. The actual temperature zones the charger operates in, can be read out from the charge status register CG_STATUS1.

Figure 38. JEITA Charging Profile

If the adapter current measured with a sense resistor between the pins ACN and ACP exceeds its programmed value or the adapter voltage measured at VACS drops below a certain level (typically 7 V, see Electrical Characteristics) the charge current is reduced automatically to avoid an overload condition of the AC adapter and an undervoltage condition for the system. The charge current is also reduced if the charger temperature measured in the IC is exceeding 100°C.

The charger indicates its current status of operation in two ways. One is the STAT output pin which can be used to drive an LED. The STAT pin can have three different states as described in Table 1. To get details about the current state of charging the charging status register CG_STATUS1 can be read.

A status change from charging suspended to charging active and back sets the interrupt CGACT and charging completed sets the interrupt CGCPL. Both interrupts can be masked. If not masked, they will trigger IRQ pin to go low when they are set.

7.3.5 DC-DC Converters

The built in DC-DC converters are completely integrated except the required passive components. To maintain high efficiency, they are implemented as synchronous step-down converters. At medium and heavy loads they are operating in a PWM mode. As soon as the inductor current gets discontinuous, which means that the output current gets lower than half of the inductor ripple current the converters enter Power Save Mode. In Power Save Mode the switching frequency decreases linearly with the load current maintaining high efficiency. The transition into and out of Power Save Mode happens within the entire regulation scheme and is seamless in both directions.

All DC-DC converters can be enabled using their ENx pins. If they should be enabled using the digital interface the enable pin function can be masked in the DCDCx_CTRL register. If masked enable only works by writing a 1 to the EN bit in the DCDCx_CTRL register.

As soon as the output voltage reaches 80% of the input voltage, the power good register bit for this converter is set to 1. If the output voltage drops below this threshold the power good bit is set back to 0.

The start-up of the converter is controlled by an internal soft-start to make sure the output voltage is built up smoothly and the inrush current during start-up is kept at minimum.

All converters are current limited. The current limit is controlling the maximum output current. If the current limit is controlling the converter its respective OLDCDCx interrupt bits are set to 1. The OLDCDCx interrupt bits can be masked. If not masked, they will trigger IRQ pin to go low when they are set.

To make sure that the output voltage of the DC-DC converters is decreasing fast to a safe low value a built in output auto-discharge function can be enabled using the ADENDCDC bit in the respective DCDCx_CTRL register. If enabled, the output capacitors are actively discharged as soon as the converter is disabled. While the converter is enabled, its output discharge circuit is off to save power.

7.3.6 Load Switches

Load switches are turned on using the digital control interface by writing 1 in the ENFETx bit of their load switch control register FETx_CTRL. They cannot be enabled before DCDC1 and DCDC2 have been started and their output voltage is above their power good level. If DCDC1 or DCDC2 will be disabled, load switches will be immediately disabled as well and enabled if both DC-DC converters are enabled again.

After being turned on, the output voltage of the load switch is ramped up with a controlled slope (<1 V / μs) . The current limit is active during that time and does not allow the current to overshoot. This means the slope can be slower if controlled by the current limit.

After being turned on, a timer is started. If the timer terminates, the output voltage must have reached the input voltage. Otherwise, the load switch is turned off again expecting an overload condition. The minimum value of the timer is 200 μs. This timer is used as well if the load switch control limits the current. The timer can be extended through the digital control interface using 4 steps (max factor 16 up to 3 ms). If the load switch has been turned off by this safety timer, the load switch can only been turned on again by reprogramming its ENFETx bit to 1 again.

As soon as the output voltage reaches 80% of the input voltage, the power good register bit for this load switch is set to 1. If the output voltage drops below this threshold, the power good bit is set back to 0.

All load switches are current limited. The current limit is regulating the maximum output current. A temperature sensor can trigger the turnoff of the load switch as well. If the current limit is controlling the switch, their respective OLFETx interrupt bits are set to 1. The OLFETx interrupt bits can be masked. If not masked, they will trigger IRQ pin to go low when they are set.

To make sure that a voltage on the output of FET2 is not supplying its input while turned off, it is reverse-current protected. This feature is only available at FET2 to support controlling circuit blocks which can get power from an external source while the system is turned off, like HDMI.

To make sure that the output voltage of the load switches is decreasing fast to a safe low value, a built-in output auto-discharge function can be enabled using the ADENFETx bit in the respective FETx_CTRL register. If enabled, the output capacitors are actively discharged as soon as the load switch is disabled. While the load switch is enabled, its output discharge circuit is off to save power.

7.3.7 ADC

Analog-to-digital conversion is controlled according to the flow chart shown in Figure 39. After enabling the ADC, the channel which should be measured must be defined in the ADC control register. Analog-to-digital conversion is started by writing the start command in the ADC register. As soon as conversion is finished, ADEOC is set to 1 and the data is available in the ADOUT registers.

Figure 39. Analog-to-Digital Conversion

7.3.8 Protection

The device has 2 built-in undervoltage detectors. If the system voltage is not high enough to safely operate the DC-DC converters, they are shut down with the higher undervoltage threshold which also sets VSYSG high as soon as the system voltage has increased above this threshold. In this condition, the LDOs are still on to supply the internal control circuitry. If the system voltage further decreases and hits the second lower undervoltage threshold, the LDOs are turned off as well and the internal control circuit is disabled. The control circuit is reset and restarted if the supply voltage increases above the lower undervoltage threshold.

The device has a built-in temperature sensor which monitors the internal IC temperature. If the temperature exceeds the programmed threshold (see Electrical Characteristics), the device stops operating. As soon as the IC temperature has decreased below the programmed threshold, it starts operating again. There is a built-in hysteresis to avoid unstable operation at IC temperatures at the overtemperature threshold.

7.3.9 Interrupts

The device monitors several internal states of power path, charger, DC-DC converters, and load switches. If any of those states changes, an interrupt can be asserted. By default, all states are masked, so any state which should generate an interrupt must be unmasked. If an unmasked state changes, it will generate an interrupt, which means the output impedance of the IRQ pin will go low, and if properly connected, the voltage will go low. What has caused the interrupt can be read out from the interrupt status registers IRQ1 and IRQ2. The interrupt will be cleared by writing a zero to the IRQ bit in the interrupt status register IRQ1. The content of the status registers are refreshed only after an interrupt has occurred.

7.5.1 I²C Interface

I²C is a 2-wire serial interface developed by NXP (formerly Philips Semiconductor) (see I²C-Bus Specification and user manual, Rev 4, 13 February 2012). The bus consists of a data line (SDA) and a clock line (SCL) with pullup structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I²C compatible devices connect to the I²C bus through open-drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on the bus under control of the master device.

TPS6509x works as a slave and supports the following data transfer modes, as defined in the I²C-Bus Specification: standard mode (100 kbps), fast-mode (400 kbps), and high-speed mode (up to 3.4 Mbps in write mode). The interface adds flexibility to the power supply solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements. Register contents are loaded when voltage is applied to TPS6509x higher than the UVLO threshold. The I²C interface is running from an internal oscillator that is automatically enabled when there is an access to the interface.

The data transfer protocol for standard and fast modes is exactly the same, therefore, they are referred to as F/S-mode in this document. The protocol for high-speed mode is different from the F/S-mode, and it is referred to as H/S-mode.

The TPS6509x supports 7-bit addressing; 10-bit addressing and general call address are not supported. The default device address is set to 1001000.The 2 LSB bits of the address are factory programmable. Contact TI about availability of different default device addresses.

All registers are set to their default value when the supply voltage is below the UVLO threshold.

7.5.1.2 H/S-Mode Protocol

When the bus is idle, both SDA and SCL lines are pulled high by the pullup devices.

The master generates a start condition followed by a valid serial byte containing HS master code 00001XXX. This transmission is made in F/S-mode at no more than 400 Kbps. No device is allowed to acknowledge the HS master code, but all devices must recognize it and switch their internal setting to support 3.4-Mbps operation.

The master then generates a repeated START condition (a repeated START condition has the same timing as the START condition). After this repeated START condition, the protocol is the same as F/S-mode, except that transmission speeds up to 3.4 Mbps are allowed. A STOP condition ends the HS-mode and switches all the internal settings of the slave devices to support the F/S-mode. Instead of using a STOP condition, repeated START conditions are used to secure the bus in HS-mode.

Trying to read data from register addresses not listed in this section results in FFh being read out.

Figure 40. START and STOP Conditions

Figure 41. Bit Transfer on the I²C-Bus

Figure 42. Acknowledge on the I²C-Bus

Figure 43. Bus Protocol

Figure 44. I²C Interface WRITE to in F/S Mode

Figure 45. I²C Interface READ from in F/S Mode

Table 2. IRQ1 Register Address: 0x00

Table 3. IRQ2 Register Address: 0x01

Table 4. IRQ1MASK Register Address: 0x02

Table 5. IRQ2MASK Register Address: 0x03

Table 6. CG_CTRL0 Register Address: 0x04

Table 7. CG_CTRL1 Register Address: 0x05

Table 8. CG_CTRL2 Register Address: 0x06

Table 9. CG_CTRL3 Register Address: 0x07

Table 10. CG_CTRL4 Register Address: 0x08

Table 11. CG_CTRL5 Register Address: 0x09

Table 12. CG_STATUS1 Register Address: 0x0A

Table 13. CG_STATUS2 Register Address: 0x0B

Table 14. DCDC1_CTRL Register Address: 0x0C

Table 15. DCDC2_CTRL Register Address: 0x0D

Table 16. DCDC3_CTRL Register Address: 0x0E

Table 17. FET1_CTRL Register Address: 0x0F

Table 18. FET2_CTRL Register Address: 0x10

Table 19. FET3_CTRL Register Address: 0x11

Table 20. FET4_CTRL Register Address: 0x12

Table 21. FET5_CTRL Register Address: 0x13

Table 22. FET6_CTRL Register Address: 0x14

Table 23. FET7_CTRL Register Address: 0x15

Table 24. AD_CTRL Register Address: 0x16

Table 25. AD_OUT1 Register Address: 0x17

Table 26. AD_OUT2 Register Address: 0x18

Table 27. SPARE2 Register Address: 0x1B