SWCS133D September 2015 – May 2019 TPS65094
PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
BUCK1 | |||||||
VIN | Power input voltage for external HSD FET | 5.6 | 13 | 21 | V | ||
VOUT | DC output voltage | Step size | 10 | mV | |||
BUCK1_VID[6:0] = 0000000 | 0 | V | |||||
BUCK1_VID[6:0] = 0000001 | 0.5 | ||||||
BUCK1_VID[6:0] = 0000010 | 0.51 | ||||||
⋮ | ⋮ | ||||||
BUCK1_VID[6:0] = 0110011 (default) | 1.00 | ||||||
⋮ | ⋮ | ||||||
BUCK1_VID[6:0] = 1110101 | 1.66 | ||||||
BUCK1_VID[6:0] = 1110110–1111111 | 1.67 | ||||||
DC output voltage accuracy | VOUT ≥ 1 V, IOUT = 100 mA to 5 A | –2% | 2% | ||||
VOUT = 0.75 V, IOUT = 100 mA to 2.1 A | –2.5% | 2.5% | |||||
VOUT ≤ 0.6 V, IOUT = 10 mA | –3.5% | 3.5% | |||||
Total output voltage accuracy (DC + ripple) in DCM | IOUT = 10 mA, VOUT ≤ 0.785 V, VSYS = 13 V | –20 | 40 | mV | |||
IOUT = 10 mA, VOUT ≤ 0.785 V, VSYS = 21 V | –20 | 55 | |||||
SR(VOUT) | Output DVS slew rate | 2.5 | 3.125 | mV/µs | |||
ILIM_LSD | Low-side output valley current limit accuracy (programmed by external resistor RLIM) | See Section 6.3.3.4, Current Limit, for details. | –15% | 15% | |||
VTH_ZC | Low-side current zero crossing detection threshold | –11 | 11 | mV | |||
ILIMREF | Source current out of ILIM1 pin | T = 25°C | 45 | 50 | 55 | µA | |
VLIM | Voltage at ILIM1 pin | VLIM = RLIM × ILIMREF | 0.2 | 2.25 | V | ||
ΔVOUT/ΔVIN | Line regulation | VOUT ≥ 1 V, IOUT = 5 A | –0.5% | 0.5% | |||
ΔVOUT/ΔIOUT | Load regulation | VIN = 13 V, VOUT ≥ 1 V,
IOUT = 0 A to 5 A, referenced to VOUT at IOUT = 5 A |
0% | 1% | |||
ΔVOUT_TR(1) | Load transient regulation | DC + AC at sense point, VIN = 13 V,
VOUT = 1.00 V, IOUT = 1.5 A to 5 A and 5 A to 1.5 A with 1 µs of tr and tf |
–50 | 50 | mV | ||
DC + AC at sense point, VIN = 13 V,
VOUT = 0.75 V, IOUT = 0.3 A to 1.5 A and 1.5 A to 0.3 A with 1 µs of tr and tf |
|||||||
VTH_PG | Power Good deassertion threshold in percentage of target VOUT | VOUT rising | 108% | ||||
VOUT falling | 92% | ||||||
VTH_HYS_PG | Power Good reassertion hysteresis entering back into VTH_PG | VOUT rising or falling | 3% | ||||
COUT | External output capacitance | Recommended amount to meet transient specification | 180 | 220 | µF | ||
LSW | External output inductance | 0.376 | 0.47 | 0.564 | µH | ||
RDSON_DRVH | Driver DRVH resistance | Source, IDRVH = –50 mA | 3 | Ω | |||
Sink, IDRVH = 50 mA | 2 | ||||||
RDSON_DRVL | Driver DRVL resistance | Source, IDRVL = –50 mA | 3 | Ω | |||
Sink, IDRVL = 50 mA | 0.4 | ||||||
RDIS | Output auto-discharge resistance | BUCK1_DIS[1:0] = 01 | 100 | Ω | |||
BUCK1_DIS[1:0] = 10 | 200 | ||||||
BUCK1_DIS[1:0] = 11 | 500 | ||||||
CBOOT | Bootstrap capacitance | 100 | nF | ||||
RON_BOOT | Bootstrap switch ON resistance | 20 | Ω | ||||
BUCK2 | |||||||
VIN | Power input voltage for external HSD FET | 5.6 | 13 | 21 | V | ||
VOUT | DC output voltage | Step size | 10 | mV | |||
BUCK2_VID[6:0] = 0000000 (default) | 0 | V | |||||
BUCK2_VID[6:0] = 0000001 | 0.5 | ||||||
BUCK2_VID[6:0] = 0000010 | 0.51 | ||||||
⋮ | ⋮ | ||||||
BUCK2_VID[6:0] = 1110101 | 1.66 | ||||||
BUCK2_VID[6:0] = 1110110–1111111 | 1.67 | ||||||
DC output voltage accuracy | VOUT ≥ 1 V, IOUT = 100 mA to 21 A | –2% | 2% | ||||
VOUT = 0.75 V, IOUT = 100 mA to 6.3 A | –2.5% | 2.5% | |||||
VOUT ≤ 0.6 V, IOUT = 10 mA | –3.5% | 3.5% | |||||
Total output voltage accuracy (DC + ripple) in DCM | IOUT = 10 mA, VOUT ≤ 0.765 V | –20 | 40 | mV | |||
SR(VOUT) | Output DVS slew rate | 2.5 | 3.125 | mV/µs | |||
ILIM_LSD | Low-side output valley current limit accuracy (programmed by external resistor RLIM) | See Section 6.3.3.4, Current Limit, for details. | –15% | 15% | |||
VTH_ZC | Low-side current zero crossing detection threshold | –11 | 11 | mV | |||
ILIMREF | Source current out of ILIM2 pin | T = 25°C | 45 | 50 | 55 | µA | |
VLIM | Voltage at ILIM2 pin | VLIM = RLIM × ILIMREF | 0.2 | 2.25 | V | ||
ΔVOUT/ΔVIN | Line regulation | VOUT ≥ 1 V, IOUT = 21 A | –0.5% | 0.5% | |||
ΔVOUT/ΔIOUT | Load regulation | VIN = 13 V, 1 V ≤ VOUT ≤ 1.3 V,
IOUT = 0 A to 21 A, referenced to VOUT at IOUT = 21 A |
0% | 1% | |||
ΔVOUT_TR(1) | Load transient regulation | DC + AC at sense point, VIN = 13 V, VOUT = 1 V,
IOUT = 1 A to 21 A and 21 A to 1 A with 1 µs of tr and tf |
–160 | 30(2) | mV | ||
DC + AC at sense point, VIN = 13 V,
VOUT = 0.75 V, IOUT = 1 A to 3.3 A and 3.3 A to 1 A with 1 µs of tr and tf |
–50 | 50(2) | |||||
VTH_PG | Power Good deassertion threshold in percentage of target VOUT | VOUT rising | 108% | ||||
VOUT falling | 92% | ||||||
VTH_HYS_PG | Power Good reassertion hysteresis entering back into VTH_PG | VOUT rising or falling | 3% | ||||
LSW | External output inductance | 0.176 | 0.22 | 0.264 | µH | ||
COUT | External output capacitance | Recommended amount to meet transient specification | 440 | 550 | µF | ||
RDSON_DRVH | Driver DRVH resistance | Source, IDRVH = –50 mA | 3 | Ω | |||
Sink, IDRVH = 50 mA | 2 | ||||||
RDSON_DRVL | Driver DRVL resistance | Source, IDRVL = –50 mA | 3 | Ω | |||
Sink, IDRVL = 50 mA | 0.4 | ||||||
RDIS | Output auto-discharge resistance | BUCK2_DIS[1:0] = 01 | 100 | Ω | |||
BUCK2_DIS[1:0] = 10 | 200 | ||||||
BUCK2_DIS[1:0] = 11 | 500 | ||||||
CBOOT | Bootstrap capacitance | 100 | nF | ||||
RON_BOOT | Bootstrap switch ON resistance | 20 | Ω | ||||
BUCK6 | |||||||
VIN | Power input voltage for external HSD FET | 5.6 | 13 | 21 | V | ||
VOUT | DC output voltage | Step size | 10 | mV | |||
BUCK6_VID[6:0] = 0000000 | 0 | V | |||||
BUCK6_VID[6:0] = 0000001 | 0.5 | ||||||
BUCK6_VID[6:0] = 0000010 | 0.51 | ||||||
⋮ | ⋮ | ||||||
BUCK6_VID[6:0] = 0111101 (TPS650940 and TPS650944 default) | 1.1 | ||||||
⋮ | ⋮ | ||||||
BUCK6_VID[6:0] = 1000111 (TPS650941 default) | 1.2 | ||||||
⋮ | ⋮ | ||||||
BUCK6_VID[6:0] = 1010110 (TPS650942 default) | 1.35 | ||||||
⋮ | ⋮ | ||||||
BUCK6_VID[6:0] = 1110101 | 1.66 | ||||||
BUCK6_VID[6:0] = 1110110–1111111 | 1.67 | ||||||
DC output voltage accuracy | VOUT ≥ 1 V, IOUT = 100 mA to 7 A | –2% | 2% | ||||
ILIM_LSD | Low-side output valley current limit accuracy (programmed by external resistor RLIM) | See Section 6.3.3.4, Current Limit, for details. | –15% | 15% | |||
VTH_ZC | Low-side current zero crossing detection threshold | –11 | 11 | mV | |||
ILIMREF | Source current out of ILIM6 pin | T = 25°C | 45 | 50 | 55 | µA | |
VLIM | Voltage at ILIM6 pin | VLIM = RLIM × ILIMREF | 0.2 | 2.25 | V | ||
ΔVOUT/ΔVIN | Line regulation | VOUT ≥ 1 V, IOUT = 7 A | –0.5% | 0.5% | |||
ΔVOUT/ΔIOUT | Load regulation | VIN = 13 V, VOUT ≥ 1 V, IOUT = 0 A to 7 A, referenced to VOUT at IOUT = 7 A | 0% | 1% | |||
ΔVOUT_TR | Load transient regulation | DC + AC at sense point, VIN = 13 V,
VOUT = 1.35 V, IOUT = 2.1 A to 7 A and 7 A to 2.1 A with 1.96 µs of tr and tf (2.5 A/µs) |
–5% | 5% | |||
VTH_PG | Power Good deassertion threshold in percentage of target VOUT | VOUT rising | 108% | ||||
VOUT falling | 92% | ||||||
VTH_HYS_PG | Power Good reassertion hysteresis entering back into VTH_PG | VOUT rising or falling | 3% | ||||
LSW | External output inductance | 0.376 | 0.47 | 0.564 | µH | ||
COUT | External output capacitance | Recommended amount to meet transient specification | 150 | 220 | µF | ||
RDSON_DRVH | Driver DRVH resistance | Source, IDRVH = –50 mA | 3 | Ω | |||
Sink, IDRVH = 50 mA | 2 | ||||||
RDSON_DRVL | Driver DRVL resistance | Source, IDRVL = –50 mA | 3 | Ω | |||
Sink, IDRVL = 50 mA | 0.4 | ||||||
RDIS | Output auto-discharge resistance | BUCK6_DIS[1:0] = 01 | 100 | Ω | |||
BUCK6_DIS[1:0] = 10 | 200 | ||||||
BUCK6_DIS[1:0] = 11 | 500 | ||||||
CBOOT | Bootstrap capacitance | 100 | nF | ||||
RON_BOOT | Bootstrap switch ON resistance | 20 | Ω |