SWCS133D September 2015 – May 2019 TPS65094
PRODUCTION DATA.
Assertion of the SLP_S4B (H → L) after the S3 entry pushes the sequence further down to S4/5 where SWB1_2 (for LPDDR3 or LPDDR4) and BUCK6 are disabled. Any rails not shown are essentially the same as the S0 to S3 entry and exit case described in Figure 6-11.