SWCS133D September   2015  – May 2019 TPS65094

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2 Revision History
  3. 3 Device Options
    1. 3.1 OTP Comparison
  4. 4 Pin Configuration and Functions
    1.     RSK Package 64-Pin VQFN With Thermal Pad Top View
    2.     Pin Functions
  5. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: Total Current Consumption
    6. 5.6  Electrical Characteristics: Reference and Monitoring System
    7. 5.7  Electrical Characteristics: Buck Controllers
    8. 5.8  Electrical Characteristics: Synchronous Buck Converters
    9. 5.9  Electrical Characteristics: LDOs
    10. 5.10 Electrical Characteristics: Load Switches
    11. 5.11 Digital Signals: I2C Interface
    12. 5.12 Digital Input Signals (LDOLS_EN, SWA1_EN, THERMTRIPB, PMICEN, SLP_S3B, SLP_S4B, SLP_S0B)
    13. 5.13 Digital Output Signals (IRQB, RSMRSTB, PCH_PWROK, PROCHOT)
    14. 5.14 Timing Requirements
    15. 5.15 Switching Characteristics
    16. 5.16 Typical Characteristics
  6. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Good (PGOOD)
      2. 6.3.2 Register Reset Conditions
      3. 6.3.3 SMPS Voltage Regulators
        1. 6.3.3.1 Controller Overview
        2. 6.3.3.2 Converter Overview
        3. 6.3.3.3 DVS
        4. 6.3.3.4 Current Limit
      4. 6.3.4 LDOs and Load Switches
        1. 6.3.4.1 VTT LDO
        2. 6.3.4.2 LDOA1–LDOA3
        3. 6.3.4.3 Load Switches
      5. 6.3.5 Power Sequencing and VR Control
        1. 6.3.5.1 Cold Boot
        2. 6.3.5.2 Cold OFF
        3. 6.3.5.3 Connected Standby Entry and Exit
        4. 6.3.5.4 S0 to S3 Entry and Exit
        5. 6.3.5.5 S0 to S4/5 Entry and Exit
        6. 6.3.5.6 Emergency Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Off Mode
      2. 6.4.2 Standby Mode
      3. 6.4.3 Active Mode
    5. 6.5 Programming
      1. 6.5.1 I2C Interface
        1. 6.5.1.1 F/S-Mode Protocol
    6. 6.6 Register Maps
      1. 6.6.1  VENDORID: PMIC Vendor ID Register (offset = 00h) [reset = 0010 0010]
        1. Table 6-12 VENDORID Register Field Descriptions
      2. 6.6.2  DEVICEID: PMIC Device and Revision ID Register (offset = 01h) [reset = OTP Dependent]
        1. Table 6-13 DEVICEID Register Field Descriptions
      3. 6.6.3  IRQ: PMIC Interrupt Register (offset = 02h) [reset = 0000 0000]
        1. Table 6-14 IRQ Register Field Descriptions
      4. 6.6.4  IRQ_MASK: PMIC Interrupt Mask Register (offset = 03h) [reset = 1111 1111]
        1. Table 6-15 IRQ_MASK Register Field Descriptions
      5. 6.6.5  PMICSTAT: PMIC Status Register (offset = 04h) [reset = 0000 0000]
        1. Table 6-16 PMICSTAT Register Field Descriptions
      6. 6.6.6  OFFONSRC: PMIC Power Transition Event Register (offset = 05h) [reset = 0000 0000]
        1. Table 6-17 OFFONSRC Register Field Descriptions
      7. 6.6.7  BUCK1CTRL: BUCK1 Control Register (offset = 20h) [reset = 0011 1000]
        1. Table 6-18 BUCK1CTRL Register Field Descriptions
      8. 6.6.8  BUCK2CTRL: BUCK2 Control Register (offset = 21h) [reset = 0000 0000]
        1. Table 6-19 BUCK2CTRL Register Field Descriptions
      9. 6.6.9  BUCK3CTRL: BUCK3 Control Register (offset = 23h) [reset = 0001 0001]
        1. Table 6-20 BUCK3CTRL Register Field Descriptions
      10. 6.6.10 BUCK4CTRL: BUCK4 Control Register (offset = 25h) [reset = OTP Dependent]
        1. Table 6-21 BUCK4CTRL Register Field Descriptions
      11. 6.6.11 BUCK5CTRL: BUCK5 Control Register (offset = 26h) [reset = OTP Dependent]
        1. Table 6-22 BUCK5CTRL Register Field Descriptions
      12. 6.6.12 BUCK6CTRL: BUCK6 Control Register (offset = 27h) [reset = 0011 1101]
        1. Table 6-23 BUCK6CTRL Register Field Descriptions
      13. 6.6.13 DISCHCNT1: Discharge Control1 Register (offset = 40h) [reset = 0101 0101]
        1. Table 6-24 DISCHCNT1 Register Field Descriptions
      14. 6.6.14 DISCHCNT2: Discharge Control2 Register (offset = 41h) [reset = 0101 0101]
        1. Table 6-25 DISCHCNT2 Register Field Descriptions
      15. 6.6.15 DISCHCNT3: Discharge Control3 Register (offset = 42h) [reset = 0000 0101]
        1. Table 6-26 DISCHCNT3 Register Field Descriptions
      16. 6.6.16 POK_DELAY: PCH_PWROK Delay Register (offset = 43h) [reset = 0000 0111]
        1. Table 6-27 POK_DELAY Register Field Descriptions
      17. 6.6.17 FORCESHUTDN: Force Emergency Shutdown Control Register (offset = 91h) [reset = 0000 0000]
        1. Table 6-28 FORCESHUTDN Register Field Descriptions
      18. 6.6.18 BUCK4VID: BUCK4 VID Register (offset = 94h) [reset = 0010 1111]
        1. Table 6-29 BUCK4VID Register Field Descriptions
      19. 6.6.19 BUCK5VID: BUCK5 VID Register (offset = 96h) [reset = 0100 1011]
        1. Table 6-30 BUCK5VID Register Field Descriptions
      20. 6.6.20 BUCK6VID: BUCK6 VID Register (offset = 98h) [reset = OTP Dependent]
        1. Table 6-31 BUCK6VID Register Field Descriptions
      21. 6.6.21 LDOA2VID: LDOA2 VID Register (offset = 9Ah) [reset = OTP Dependent]
        1. Table 6-32 LDOA2VID Register Field Descriptions
      22. 6.6.22 LDOA3VID: LDOA3 VID Register (offset = 9Bh) [reset = OTP Dependent]
        1. Table 6-33 LDOA3VID Register Field Descriptions
      23. 6.6.23 VR_CTRL1: BUCK1-3 Control Register (offset = 9Ch) [reset = OTP Dependent]
        1. Table 6-34 VR_CTRL1 Register Field Descriptions
      24. 6.6.24 VR_CTRL2: VR Enable Register (offset = 9Eh) [reset = 0000 0000]
        1. Table 6-35 VR_CTRL2 Register Field Descriptions
      25. 6.6.25 VR_CTRL3: VR Enable/Disable Register (offset = 9Fh) [reset = OTP Dependent]
        1. Table 6-36 VR_CTRL3 Register Field Descriptions
      26. 6.6.26 GPO_CTRL: GPO Control Register (offset = A1h) [reset = 0010 0000]
        1. Table 6-37 GPO_CTRL Register Field Descriptions
      27. 6.6.27 PWR_FAULT_MASK1: VR Power Fault Mask1 Register (offset = A2h) [reset = 1100 0000]
        1. Table 6-38 PWR_FAULT_MASK1 Register Field Descriptions
      28. 6.6.28 PWR_FAULT_MASK2: VR Power Fault Mask2 Register (offset = A3h) [reset = 0011 0111]
        1. Table 6-39 PWR_FAULT_MASK2 Register Field Descriptions
      29. 6.6.29 DISCHCNT4: Discharge Control4 Register (offset = ADh) [reset = 0110 0001]
        1. Table 6-40 DISCHNT4 Register Field Descriptions
      30. 6.6.30 LDOA1CTRL: LDOA1 Control Register (offset = AEh) [reset = OTP Dependent]
        1. Table 6-41 LDOA1CTRL Register Field Descriptions
      31. 6.6.31 PG_STATUS1: Power Good Status1 Register (offset = B0h) [reset = 0000 0000]
        1. Table 6-42 PG_STATUS1 Register Field Descriptions
      32. 6.6.32 PG_STATUS2: Power Good Status2 Register (offset = B1h) [reset = 0000 0000]
        1. Table 6-43 PG_STATUS2 Register Field Descriptions
        2. 6.6.32.1   PWR_FAULT_STATUS1: Power Fault Status1 Register (offset = B2h) [reset = 0000 0000]
          1. Table 6-44 PWR_FAULT_STATUS1 Register Field Descriptions
        3. 6.6.32.2   PWR_FAULT_STATUS2: Power Fault Status2 Register (offset = B3h) [reset = 0000 0000]
          1. Table 6-45 PWR_FAULT_STATUS2 Register Field Descriptions
      33. 6.6.33 TEMPHOT: Temperature Hot Status Register (offset = B5h) [reset = 0000 0000]
        1. Table 6-46 TEMPHOT Register Field Descriptions
  7. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Controller Design Procedure
          1. 7.2.2.1.1 Selecting the Output Capacitors
          2. 7.2.2.1.2 Selecting the Inductor
          3. 7.2.2.1.3 Selecting the FETs
          4. 7.2.2.1.4 Bootstrap Capacitor
          5. 7.2.2.1.5 Selecting the Input Capacitors
            1. 7.2.2.1.5.1 Setting the Current Limit
        2. 7.2.2.2 Converter Design Procedure
          1. 7.2.2.2.1 Selecting the Inductor
          2. 7.2.2.2.2 Selecting the Output Capacitors
          3. 7.2.2.2.3 Selecting the Input Capacitors
        3. 7.2.2.3 LDO Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Specific Application for TPS650944
    4. 7.4 Do's and Don'ts
  8. 8 Power Supply Recommendations
  9. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Development Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Community Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.3 SMPS Voltage Regulators

The buck controllers integrate gate drivers for external power stages with programmable current limit (set by an external resistor at ILIMx pin), which allows for optimal selection of external passive components based on the desired system load. The buck converters include integrated power stage and require a minimum number of pins for power input, inductor, and output voltage feedback input. Combined with high-frequency switching, all these features allow use of inductors in small form factor, thus reducing the total cost and size of the system.

BUCK3–BUCK6 have selectable auto- and forced-PWM mode through the BUCKx_MODE bit in the BUCKxCTRL register. In default auto mode, the VR automatically switches between PWM and PFM depending on the output load to maximize efficiency. The host cannot select Forced PWM mode for other SMPS VRs as they stay in auto mode at all times.

See Table 6-3 and Table 6-4 for the full voltage tables for all SMPS regulators.

Table 6-3 10-mV Step-Size VOUT Range (BUCK1, BUCK2, BUCK5, BUCK6)

VID Bits VOUT VID Bits VOUT VID Bits VOUT
0000000 0 0101011 0.92 1010110 1.35
0000001 0.50 0101100 0.93 1010111 1.36
0000010 0.51 0101101 0.94 1011000 1.37
0000011 0.52 0101110 0.95 1011001 1.38
0000100 0.53 0101111 0.96 1011010 1.39
0000101 0.54 0110000 0.97 1011011 1.40
0000110 0.55 0110001 0.98 1011100 1.41
0000111 0.56 0110010 0.99 1011101 1.42
0001000 0.57 0110011 1.00 1011110 1.43
0001001 0.58 0110100 1.01 1011111 1.44
0001010 0.59 0110101 1.02 1100000 1.45
0001011 0.60 0110110 1.03 1100001 1.46
0001100 0.61 0110111 1.04 1100010 1.47
0001101 0.62 0111000 1.05 1100011 1.48
0001110 0.63 0111001 1.06 1100100 1.49
0001111 0.64 0111010 1.07 1100101 1.50
0010000 0.65 0111011 1.08 1100110 1.51
0010001 0.66 0111100 1.09 1100111 1.52
0010010 0.67 0111101 1.10 1101000 1.53
0010011 0.68 0111110 1.11 1101001 1.54
0010100 0.69 0111111 1.12 1101010 1.55
0010101 0.70 1000000 1.13 1101011 1.56
0010110 0.71 1000001 1.14 1101100 1.57
0010111 0.72 1000010 1.15 1101101 1.58
0011000 0.73 1000011 1.16 1101110 1.59
0011001 0.74 1000100 1.17 1101111 1.60
0011010 0.75 1000101 1.18 1110000 1.61
0011011 0.76 1000110 1.19 1110001 1.62
0011100 0.77 1000111 1.20 1110010 1.63
0011101 0.78 1001000 1.21 1110011 1.64
0011110 0.79 1001001 1.22 1110100 1.65
0011111 0.80 1001010 1.23 1110101 1.66
0100000 0.81 1001011 1.24 1110110 1.67
0100001 0.82 1001100 1.25 1110111 1.67
0100010 0.83 1001101 1.26 1111000 1.67
0100011 0.84 1001110 1.27 1111001 1.67
0100100 0.85 1001111 1.28 1111010 1.67
0100101 0.86 1010000 1.29 1111011 1.67
0100110 0.87 1010001 1.30 1111100 1.67
0100111 0.88 1010010 1.31 1111101 1.67
0101000 0.89 1010011 1.32 1111110 1.67
0101001 0.90 1010100 1.33 1111111 1.67
0101010 0.91 1010101 1.34

Table 6-4 25-mV Step-Size VOUT Range (BUCK3, BUCK4)

VID Bits VOUT VID Bits VOUT VID Bits VOUT
0000000 0 0101011 1.700 1010110 2.775
0000001 0.650 0101100 1.725 1010111 2.800
0000010 0.675 0101101 1.750 1011000 2.825
0000011 0.700 0101110 1.775 1011001 2.850
0000100 0.725 0101111 1.800 1011010 2.875
0000101 0.750 0110000 1.825 1011011 2.900
0000110 0.775 0110001 1.850 1011100 2.925
0000111 0.800 0110010 1.875 1011101 2.950
0001000 0.825 0110011 1.900 1011110 2.975
0001001 0.850 0110100 1.925 1011111 3.000
0001010 0.875 0110101 1.950 1100000 3.025
0001011 0.900 0110110 1.975 1100001 3.050
0001100 0.925 0110111 2.000 1100010 3.075
0001101 0.950 0111000 2.025 1100011 3.100
0001110 0.975 0111001 2.050 1100100 3.125
0001111 1.000 0111010 2.075 1100101 3.150
0010000 1.025 0111011 2.100 1100110 3.175
0010001 1.050 0111100 2.125 1100111 3.200
0010010 1.075 0111101 2.150 1101000 3.225
0010011 1.100 0111110 2.175 1101001 3.250
0010100 1.125 0111111 2.200 1101010 3.275
0010101 1.150 1000000 2.225 1101011 3.300
0010110 1.175 1000001 2.250 1101100 3.325
0010111 1.200 1000010 2.275 1101101 3.350
0011000 1.225 1000011 2.300 1101110 3.375
0011001 1.250 1000100 2.325 1101111 3.400
0011010 1.275 1000101 2.350 1110000 3.425
0011011 1.300 1000110 2.375 1110001 3.450
0011100 1.325 1000111 2.400 1110010 3.475
0011101 1.350 1001000 2.425 1110011 3.500
0011110 1.375 1001001 2.450 1110100 3.525
0011111 1.400 1001010 2.475 1110101 3.550
0100000 1.425 1001011 2.500 1110110 3.575
0100001 1.450 1001100 2.525 1110111 3.575
0100010 1.475 1001101 2.550 1111000 3.575
0100011 1.500 1001110 2.575 1111001 3.575
0100100 1.525 1001111 2.600 1111010 3.575
0100101 1.550 1010000 2.625 1111011 3.575
0100110 1.575 1010001 2.650 1111100 3.575
0100111 1.600 1010010 2.675 1111101 3.575
0101000 1.625 1010011 2.700 1111110 3.575
0101001 1.650 1010100 2.725 1111111 3.575
0101010 1.675 1010101 2.750