SLVSB04A July 2011 – August 2015 TPS65186
PRODUCTION DATA.
The TPS65186 device provides two adjustable LDOs, inverting buck-boost converter, boost converter, thermistor monitoring, and flexible power-up and power-down sequencing. The system can be supplied by a regulated input voltage ranging from 3 V to 6 V. The device is characterized across a –10°C to 85°C temperature range, best suited for personal electronic applications.
The I2C interface provides comprehensive features for using the TPS65186. All rails can be enabled or disabled. Power-up and power-down sequences can also be programmed through the I2C interface, as well as thermistor configuration and interrupt configuration. Voltage adjustment can also be controlled by the I2C interface.
The adjustable LDOs can supply up to 120 mA of current. The default output voltages for each LDO can be adjusted through the I2C interface. LDO1 (VPOS) and LDO2 (VNEG) track each other in a way that they are of opposite sign but same magnitude. The sum of VLDO1 and VLOD2 is guaranteed to be less than 50 mV.
There are two charge pumps: VDDH and VEE 10 mA and 12 mA respectively. These charge pumps boost the DC-DC boost converters ±16-V rails to provide a gate channel supply.
The power good functionality is open-drain output, if any of the four power rails (CP1, CP2, LDO1, LDO2) are not in regulation, encounters a fault, or is disabled the pin is pulled low. PWR_GOOD remains low if one of the rails is not enabled by the host and only after all rails are in regulation PWR_GOOD is released to Hi-Z state (pulled up by external resistor).
The TPS65186 provides circuitry to bias and measure an external NTC to monitor the display panel temperature in a range from –10°C to 85°C with and accuracy of ±1°C from 0°C to 50°C. Temperature measurement are triggered by the controlling host and the last temperature reading is always stored in the TMST_VALUE register. Interrupts are issued when the temperature exceeds the programmable HOT, or drops below the programmable COLD threshold, or when the temperature has changed by more than a user-defined threshold from the baseline value.
This device is offered in a 48-Pin, 0.5-mm Pitch, 7 mm × 7 mm × 0.9 mm (VQFN) RGZ package.
The power-up and power-down order and timing is defined by user register settings. The default settings support the E Ink Vizplex panel and typically do not need to be changed.
In SLEEP mode the TPS65186 is completely turned off, the I2C registers are reset, and the device does not accept any I2C transaction. Pull the WAKEUP pin high with the PWRUP pin low and the device enters STANDBY mode that enables the I2C interface. Write to the UPSEQ0 register to define the order in which the output rails are enabled at power-up and to the UPSEQ1 registers to define the power-up delays between rails. Finally, set the ACTIVE bit in the ENABLE register to 1 to execute the power-up sequence and bring up all power rails. Alternatively, pull the PWRUP pin high (rising edge).
After the ACTIVE bit has been set, the negative boost converter (VN) is powered up first, followed by the positive boost (VB). The positive boost enable is gated by the internal power-good signal of the negative boost. Once VB is in regulation, it issues an internal power-good signal and after delay time UDLY1 has expired, STROBE1 is issued. The rail assigned to STROBE1 will power up next and after its power-good signal has been asserted and delay time UDLY2 has expired, STROBE2 is issued. The sequence continues until STROBE4 has occurred and the last rail has been enabled.
To power down the device, set the STANDBY bit of the ENABLE register to 1 or pull the PWRUP pin low (falling edge) and the TPS65186 will power down in the order defined by DWNSEQx registers. The delay times DDLY2, DDLY3, and DDLY4 are weighted by a factor of DFCTR which allows the user to space out the power down of the rails to avoid crossing during discharge. DFCTR is located in register DWNSEQ1. The positive boost (VB) is shut down together with the last rail at STROBE4. However, the negative boost (VN) remains up and running for another 50 ms. Then VN is powered down and the device enters STANDBY or SLEEP mode, depending on the WAKEUP pin.
If either the ACTIVE bit is set or the PWRUP pin is pulled high while the device is powering down, the power-down sequence (STROBE1-4) is completed first, followed by a power-up sequence. VB and VN may or may not be powered down and depending on the relative timing of STROBE4 to the new power-up event.
During power-up, if the STANDBY bit is set or the PWRUP pin is pulled low, the power-up sequence is aborted and the power-down sequence starts immediately.
Charge pumps, LDOs, and VCOM driver are dependent on the positive and inverting buck-boost converters and several dependencies exist that affect the power-up sequencing. These dependencies are the following:
TPS65186 supports soft start for all rails, that is, inrush current is limited during startup of DCDC1, DCDC2, LDO1, LDO2, CP1, and CP2. If DCDC1 or DCDC2 are unable to reach power-good status within 50 ms, the corresponding UV flag is set in the interrupt registers, the interrupt pin is pulled low, and the device enters STANDBY mode. LDO1, LDO2, positive and negative charge pumps also have a 50-ms power-good time-out limit. If either rail is unable to power up within 50 ms after it has been enabled, the corresponding UV flag is set and the interrupt pin is pulled low. However, the device will remain in ACTIVE mode in this case.
LDO1 (VPOS) and LDO2 (VNEG) track each other in a way that they are of opposite sign but same magnitude. The sum of VLDO1 and VLOD2 is guaranteed to be less than 50 mV.
The integrated power switch is used to cut the 3.3-V supply to the EPD panel and is controlled through the V3P3_EN pin of the ENABLE register. In SLEEP mode the switch is automatically turned off and its output is discharged to ground. The default power-up state is OFF. To turn the switch ON, set the V3P3_ENbit to 1.
VCOM is the output of a power-amplifier with an output voltage range of 0 V to –5.11 V, adjustable in 10-mV steps. In a typical application VCOM is connected to the VCOM terminal of the EPD panel and the amplifier is controlled through the VCOM_CTRL pin. With VCOM_CTRL high, the amplifier drives the VCOM pin to the voltage specified by the VCOM1 and VCOM2 register.
For ease of design, the VCOM_CTRL pin may also be tied to the battery or IO supply. In this case, VCOM is enabled with STROBE4 during the power-up sequence and disabled on STROBE1 of the power-down sequence. Therefore VCOM is the last rail to be enabled and the first to be disabled.
TPS65186 can perform a voltage measurement on the VCOM pin to deter87/mine the kick-back voltage of the panel. This allows in-system calibration of VCOM. To perform a kick-back voltage measurement, follow these steps:
The measurement result is not automatically programmed into nonvolatile memory. Changing the power-up default is described in Storing the VCOM Power-Up Default Value in Memory.
The power-up default value of VCOM can be user-set and programmed into nonvolatile memory. To do so, write the default value to the VCOM[8:0] bits of the VCOM1 and VCOM2 register, then set the PROG bit in VCOM2 register to 1. First, all power rails are shut down, then the VCOM[8:0] value is committed to nonvolatile memory such that it becomes the new power-up default. Once programming is complete, the PRGC bit in the INT1 register is set and the nINT pin is pulled low. To verify that the new value has been saved properly, first write the VCOM[8:0] bits to 0x000h, then pull the WAKEUP pin low. After the WAKEUP pin is pulled back high, read the VCOM[8:0] bits to verify that the new default value is correct.
The TPS65186 monitors input/output voltages and die temperature; the device will take action if operating conditions are outside normal limits when the following are encountered:
The TPS65186 shuts down all power rails and enters STANDBY mode. Shutdown follows the order defined by DWNSEQx registers. The exception is VCOM fault witch leads to immediate shutdown of all rails. Once a fault is detected, the PWR_GOOD and nINT pins are pulled low and the corresponding interrupt bit is set in the interrupt register. Power rails cannot be re-enabled unless the interrupt bits have been cleared by reading the INT1 and INT2 register. Alternatively, toggling the WAKEUP pin also resets the interrupt bits. As the PWRUP input is edge sensitive, the host must toggle the PWRUP pin to re-enable the rails through GPIO control, that is, it must bring the PWRUP pin low before asserting it again. Alternatively rails can be re-enbled through the I2C interface.
Whenever the TPS65186 encounters undervoltage on VNEG (VNEG_UV), VPOS (VPOS_UV), VEE (VEE_UV), or VDDH (VDDH_UV), rails are not shut down but the PWR_GOOD and nINT is pulled low with the corresponding interrupt bit set. The device remains in ACTIVE mode and recovers automatically once the fault has been removed.
The power good pin (PWR_GOOD) is an open-drain output that is pulled high (by an external pullup resistor) when all four power rails (CP1, CP2, LDO1, LDO2) are in regulation and is pulled low if any of the rails encounters a fault or is disabled. PWR_GOOD remains low if one of the rails is not enabled by the host and only after all rails are in regulation PWR_GOOD is released to Hi-Z state (pulled up by external resistor).
The interrupt pin (nINT) is an open-drain output that is pulled low whenever one or more of the INT1 or INT2 bits are set. The nINT pin is released (returns to Hi-Z state) and fault bits are cleared once the register with the set bit has been read by the host. If the fault persists, the nINT pin will be pulled low again after a maximum of 32 µs.
Interrupt events can be masked by re-setting the corresponding enable bit in the INT_EN1 and INT_EN2 register, that is, the user can determine which events cause the nINT pin to be pulled low. The status of the enable bits affects the nINT pin only and has no effect on any of the protection and monitoring circuits or the INT1/INT2 bits themselves.
Persisting faults such as thermal shutdown can cause the nINT pin to be pulled low for an extended period of time which can keep the host in a loop trying to resolve the interrupt. If this behavior is not desired, set the corresponding mask bit after receiving the interrupt and keep polling the INT1/INT2 register to see when the fault condition has disappeared. After the fault is resolved, unmask the interrupt bit again.
The TPS65186 provides circuitry to bias and measure an external Negative Temperature Coefficient Resistor (NTC) to monitor the display panel temperature in a range from –10°C to 85°C with and accuracy of ±1°C from 0°C to 50°C. Temperature measurement must be triggered by the controlling host and the last temperature reading is always stored in the TMST_VALUE register. Interrupts are issued when the temperature exceeds the programmable HOT, or drops below the programmable COLD threshold, or when the temperature has changed by more than a user-defined threshold from the baseline value. Details are explained under Hot, Cold, and Temperature-Change Interrupts.
Figure 23 shows the block diagram of the NTC bias and measurement circuit. The NTC is biased from an internally generated 2.25-V reference voltage through an integrated 7.307-kΩ bias resistor. A 43-kΩ resistor is connected parallel to the NTC to linearize the temperature response curve. The circuit is designed to work with a nominal 10-kΩ NTC and achieves accuracy of ±1°C from 0°C to 50°C. The voltage drop across the NTC is digitized by a 10-bit SAR ADC and translated into an 8-bit two’s complement by digital per Table 1.
TEMPERATURE | TMST_VALUE[7:0] |
---|---|
< –10°C | 1111 0110 |
–10°C | 1111 0110 |
–9°C | 1111 0111 |
... | ... |
–2°C | 1111 1110 |
–1°C | 1111 1111 |
0°C | 0000 0000 |
1°C | 0000 0001 |
2°C | 0000 0010 |
... | ... |
25°C | 0001 1001 |
... | |
85°C | 0101 0101 |
> 85°C | 0101 0101 |
A temperature measurement is triggered by setting the READ_THERM bit of the TMST1 register to 1.During the A/D conversion the CONV_END bit of the TMST1 register reads 0, otherwise it reads 1. At the end of the A/D conversion the EOC bit in the INT2 register is set and the temperature value is available in the TMST_VALUE register.
Each temperature acquisition is compared against the programmable TMST_HOT and TMST_COLD thresholds and to the baseline temperature, to determine if the display is within allowed operating temperature range and if the temperature has changed by more than a user-defined threshold since the last update. The first temperature reading after the WAKEUP pin has been pulled high automatically becomes the baseline temperature. Any subsequent reading is compared against the baseline temperature. If the difference is equal or greater than the threshold value, an interrupt is issued (DTX bit in register INT1 is set to 1) and the latest value becomes the new baseline. If the difference is less than the threshold value, no action is taken. The threshold value is defined by DT[1:0] bits in the TMST1 register and has a default value of ±2°C. In summary:
In a typical application the temperature monitor and interrupts are used in the following manner:
The TPS65186 has three modes of operation, SLEEP, STANDBY, and ACTIVE. SLEEP mode is the lowest-power mode in which all internal circuitry is turned off. In STANDBY, all power rails are shut down but the device is ready to accept commands through the I2C interface. In ACTIVE mode one or more power rails are enabled.
This is the lowest power mode of operation. All internal circuitry is turned off, registers are reset to default values and the device does not respond to I2C communications. TPS65186 enters SLEEP mode whenever WAKEUP pin is pulled low.
In STANDBY all internal support circuitry is powered up and the device is ready to accept commands through the I2C interface but none of the power rails are enabled. The device enters STANDBY mode when the WAKEUP pin is pulled high and either the PWRUP pin is pulled low or the STANDBY bit is set. The device also enters STANDBY mode if input undervoltage lockout (UVLO), positive boost undervoltage (VB_UV), or inverting buck-boost undervoltage (VN_UV) is detected, thermal shutdown occurs, or the PROG bit is set (see Figure 22)
The device is in ACTIVE mode when any of the output rails are enabled and no fault condition is present. This is the normal mode of operation while the device is powered up.
WAKEUP pin is pulled high with PWRUP pin high. Rails come up in the order defined by the UPSEQx registers (OK to tie WAKEUP and PWRUP pin together).
WAKEUP pin is pulled high with PWRUP pin low. Rails will remain powered down.
WAKEUP pin is high and PWRRUP pin is pulled high (rising edge) or the ACTIVE bit is set. Output rails will power up in the order defined by the UPSEQx registers.
WAKEUP pin is high and STANDBY bit is set or PWRUP pin is pulled low (falling edge). Rails are shut down in the order defined by DWNSEQx registers. Device also enters STANDBY in the event of thermal shutdown (TSD), undervoltage lockout (UVLO), positive boost or inverting buck-boost undervoltage (UV), VCOM fault (VCOMF), or when the PROG bit is set (see Figure 22).
WAKEUP pin is pulled low while none of the output rails are enabled.
WAKEUP pin is pulled low while at least one output rail is enabled. Rails are shut down in the order defined by DWNSEQx registers.
The TPS65186 hosts a slave I2C interface that supports data rates up to 400 kbit/s and auto-increment addressing and is compliant to I2C standard 3.0.
The I2C Bus is a communications link between a controller and a series of slave terminals. The link is established using a two-wire bus consisting of a serial clock signal (SCL) and a serial data signal (SDA). The serial clock is sourced from the controller in all cases where the serial data line is bidirectional for data communication between the controller and the slave terminals. Each device has an open drain output to transmit data on the serial data line. An external pullup resistor must be placed on the serial data line to pull the drain output high during data transmission.
Data transmission is initiated with a start bit from the controller as shown in Figure 27. The start condition is recognized when the SDA line transitions from high to low during the high portion of the SCL signal. Upon reception of a start bit, the device will receive serial data on the SDA input and check for valid address and control information. If the appropriate slave address bits are set for the device, then the device will issue an acknowledge pulse and prepare to receive the register address. Depending on the R/nW bit, the next byte received from the master is written to the addressed register (R/nW = 0) or the device responds with 8-bit data from the register (R/nW = 1). Data transmission is completed by either the reception of a stop condition or the reception of the data word sent to the device. A stop condition is recognized as a low to high transition of the SDA input during the high portion of the SCL signal. All other transitions of the SDA line must occur during the low portion of the SCL signal. An acknowledge is issued after the reception of valid address, sub-address and data words. The I2C interfaces will auto-sequence through register addresses, so that multiple data words can be sent for a given I2C transmission. See Figure 26 and Figure 27 for details.
REGISTER | ADDRESS (HEX) | NAME | DESCRIPTION |
---|---|---|---|
0 | 0x00 | TMST_VALUE | Thermistor value read by ADC |
1 | 0x01 | ENABLE | Enable/disable bits for regulators |
2 | 0x02 | VADJ | VPOS/VNEG voltage adjustment |
3 | 0x03 | VCOM1 | Voltage settings for VCOM |
4 | 0x04 | VCOM2 | Voltage settings for VCOM + control |
5 | 0x05 | INT_EN1 | Interrupt enable group1 |
6 | 0x06 | INT_EN2 | Interrupt enable group2 |
7 | 0x07 | INT1 | Interrupt group1 |
8 | 0x08 | INT2 | Interrupt group2 |
9 | 0x09 | UPSEQ0 | Power-up strobe assignment |
10 | 0x0A | UPSEQ1 | Power-up sequence delay times |
11 | 0x0B | DWNSEQ0 | Power-down strobe assignment |
12 | 0x0C | DWNSEQ1 | Power-down sequence delay times |
13 | 0x0D | TMST1 | Thermistor configuration |
14 | 0x0E | TMST2 | Thermistor hot temp set |
15 | 0x0F | PG | Power good status each rails |
16 | 0x10 | REVID | Device revision ID information |
DATA BIT | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
---|---|---|---|---|---|---|---|---|
FIELD NAME | TMST_VALUE[7:0] | |||||||
READ/WRITE | R | R | R | R | R | R | R | R |
RESET VALUE | N/A | N/A | N/A | N/A | N/A | N/A | N/A | N/A |
FIELD NAME | BIT DEFINITION |
---|---|
TMST_VALUE[7:0] | Temperature read-out |
1111 0110 – < -10°C | |
1111 0110 – -10°C | |
1111 0111 – -9°C | |
... | |
1111 1110 – -2°C | |
1111 1111 – -1 °C | |
0000 0000 – 0 °C | |
0000 0001 – 1°C | |
0000 0010 – 2°C | |
... | |
0001 1001 – 25°C | |
... | |
0101 0101 – 85°C | |
0101 0101 – > 85°C |
DATA BIT | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
---|---|---|---|---|---|---|---|---|
FIELD NAME | ACTIVE | STANDBY | V3P3_EN | VCOM_EN | VDDH_EN | VPOS_EN | VEE_EN | VNEG_EN |
READ/WRITE | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
RESET VALUE | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
FIELD NAME | BIT DEFINITION(1) |
---|---|
ACTIVE | STANDBY to ACTIVE transition bit |
1 – Transition from STANDBY to ACTIVE mode. Rails power up as defined by UPSEQx registers | |
0 – no effect | |
NOTE: After transition bit is cleared automatically | |
STANDBY | STANDBY to ACTIVE transition bit |
1 – Transition from STANDBY to ACTIVE mode. Rails power up as defined by DWNSEQx registers | |
0 – no effect | |
NOTE: After transition bit is cleared automatically. STANDBY bit has priority over AVTIVE. | |
V3P3_EN | VIN3P3 to V3P3 switch enable |
1 – switch is ON | |
0 – switch is OFF | |
VCOM_EN | VCOM buffer enable |
1 – enabled | |
0 – disabled | |
VDDH_EN | VDDH charge pump enable |
1 – enabled | |
0 – disabled | |
VPOS_EN | VPOS LDO regulator enable |
1 – enabled | |
0 – disabled | |
NOTE: VPOS cannot be enabled before VNEG is enabled. | |
VEE_EN | VEE charge pump enable |
1 – enabled | |
0 – disabled | |
VNEG_EN | VNEG LDO regulator enable |
1 – enabled | |
0 – disabled | |
NOTE: When VNEG is disabled VPOS will also be disabled. |
DATA BIT | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
---|---|---|---|---|---|---|---|---|
FIELD NAME | not used | not used | not used | not used | not used | VSET[2:0] | ||
READ/WRITE | R/W | R/W | R/W | R/W | R | R/W | R/W | R/W |
RESET VALUE | 0 | 0 | 1 | 0 | 0 | 0E2 | 1E2 | 1E2 |
FIELD NAME | BIT DEFINITION |
---|---|
not used | N/A |
not used | N/A |
not used | N/A |
not used | N/A |
not used | N/A |
VSET[2:0] | VPOS and VNEG voltage setting |
000 - not valid | |
001 - not valid | |
010 - not valid | |
011 - ±15.000 V | |
100 - ±14.750 V | |
101 - ±14.500 V | |
110 - ±14.250 V | |
111 - reserved |
DATA BIT | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
---|---|---|---|---|---|---|---|---|
FIELD NAME | VCOM [7:0] | |||||||
READ/WRITE | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
RESET VALUE | 0E2 | 1E2 | 1E2 | 1E2 | 1 | 1 | 0 | 1 |
FIELD NAME | BIT DEFINITION |
---|---|
VCOM[7:0] | VCOM voltage, least significant byte. See VCOM 2 (VCOM2) for details. |
DATA BIT | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
---|---|---|---|---|---|---|---|---|
FIELD NAME | ACQ | PROG | HiZ | AVG[1:0] | not used | not used | VCOM[8] | |
READ/WRITE | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
RESET VALUE | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0E2 |
FIELD NAME | BIT DEFINITION |
---|---|
ACQ | Kick-back voltage acquisition bit |
1 – starts kick-back voltage measurement routine | |
0 – no effect | |
NOTE: After measurement is complete bit is cleared automatically and measurement result is reflected in VCOM[8:0] bits. | |
PROG | VCOM programming bit |
1 – VCOM[8:0] value is committed to nonvolatile memory and becomes new power-up default | |
0 – no effect | |
NOTE: After programming bit is cleared automatically and TPS65186 will enter STANDBY mode. | |
HiZ | VCOM HiZ bit |
1 – VCOM pin is placed into hi-impedance state to allow VCOM measurement | |
0 – VCOM amplifier is connected to VCOM pin | |
AVG[1:0] | Number of acquisitions that is averaged to a single kick-back voltage measurement |
00 – 1x | |
01 – 2x | |
10 – 4x | |
11 – 8x | |
NOTE: When the ACQ bit is set, the state machine repeat the A/D conversion of the kick-back voltage AVD[1:0] times and returns a single, averaged, value to VCOM[8:0] | |
not used | N/A |
not used | N/A |
VCOM[8:0] | VCOM voltage adjustment |
VCOM = VCOM[8:0] x -10 mV in the range from 0 mV to –5.110 V | |
0x000h – 0 0000 0000 – –0 mV | |
0x001h – 0 0000 0001 – –10 mV | |
0x002h – 0 0000 0010 – –20 mV | |
... | |
0x07Dh - 0 0111 1101 – –1250 mV | |
... | |
0x1FEh – 1 1111 1110 – –5100 mV | |
0x1FFh – 1 1111 1111 – –5110 mV |
DATA BIT | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
---|---|---|---|---|---|---|---|---|
FIELD NAME | DTX_EN | TSD_EN | HOT_EN | TMST_HOT_EN | TMST_COLD_EN | UVLO_EN | ACQC_EN | PRGC_EN |
READ/WRITE | R | R/W | R/W | R/W | R/W | R/W | R | R |
RESET VALUE | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
FIELD NAME | BIT DEFINITION(1) |
---|---|
DTX_EN | Panel temperature-change interrupt enable |
1 – enabled | |
0 – disabled | |
TSD_EN | Thermal shutdown interrupt enable |
1 – enabled | |
0 – disabled | |
HOT_EN | Thermal shutdown early warning enable |
1 – enabled | |
0 – disabled | |
TMST_HOT_EN | Thermistor hot interrupt enable |
1 – enabled | |
0 – disabled | |
TMST_COLD_EN | Thermistor cold interrupt enable |
1 – enabled | |
0 – disabled | |
UVLO_EN | VIN undervoltage detect interrupt enable |
1 – enabled | |
0 – disabled | |
ACQC_EN | VCOM acquisition complete interrupt enable |
1 – enabled | |
0 – disabled | |
PRGC_EN | VCOM programming complete interrupt enable |
1 – enabled | |
0 – disabled |
DATA BIT | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
---|---|---|---|---|---|---|---|---|
FIELD NAME | VBUVEN | VDDHUVEN | VNUV_EN | VPOSUVEN | VEEUVEN | VCOMFEN | VNEGUVEN | EOCEN |
READ/WRITE | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
RESET VALUE | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
FIELD NAME | BIT DEFINITION(1) |
---|---|
VBUVEN | Positive boost converter undervoltage detect interrupt enable |
1 – enabled | |
0 – disabled | |
VDDHUVEN | VDDH undervoltage detect interrupt enable |
1 – enabled | |
0 – disabled | |
VNUVEN | Inverting buck-boost converter undervoltage detect interrupt enable |
1 – enabled | |
0 – disabled | |
VPOSUVEN | VPOS undervoltage detect interrupt enable |
1 – enabled | |
0 – disabled | |
VEEUVEN | VEE undervoltage detect interrupt enable |
1 – enabled | |
0 – disabled | |
VCOMFEN | VCOM FAULT interrupt enable |
1 – enabled | |
0 – disabled | |
VNEGUVEN | VNEG undervoltage detect interrupt enable |
1 – enabled | |
0 – disabled | |
EOCEN | Temperature ADC end of conversion interrupt enable |
1 – enabled | |
0 – disabled |
DATA BIT | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
---|---|---|---|---|---|---|---|---|
FIELD NAME | DTX | TSD | HOT | TMST_HOT | TMST_COLD | UVLO | ACQC | PRGC |
READ/WRITE | R | R | R | R | R | R | R | R |
RESET VALUE | 0 | N/A | N/A | N/A | N/A | N/A | 0 | 0 |
FIELD NAME | BIT DEFINITION |
---|---|
DTX | Panel temperature-change interrupt |
1 – temperature has changed by 3 deg or more over previous reading | |
0 – no significance | |
TSD | Thermal shutdown interrupt |
1 – chip is in overtemperature shutdown | |
0 – no fault | |
HOT | Thermal shutdown early warning |
1 – chip is approaching overtemperature shutdown | |
0 – no fault | |
TMST_HOT | Thermistor hot interrupt |
1 – thermistor temperature is equal or greater than TMST_HOT threshold | |
0 – no fault | |
TMST_COLD | Thermistor cold interrupt |
1 – thermistor temperature is equal or less than TMST_COLD threshold | |
0 – no fault | |
UVLO | VIN undervoltage detect interrupt |
1 – input voltage is below UVLO threshold | |
0 – no fault | |
ACQC | VCOM acquisition complete |
1 – VCOM measurement is compete | |
0 – no significance | |
PRGC | VCOM programming complete |
1 – VCOM programming is complete | |
0 – no significance |
DATA BIT | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
---|---|---|---|---|---|---|---|---|
FIELD NAME | VB_UV | VDDH_UV | VN_UV | VPOS_UV | VEE_UV | VCOMF | VNEG_UV | EOC |
READ/WRITE | R | R | R | R | R | R | R | R |
RESET VALUE | N/A | N/A | N/A | N/A | N/A | N/A | N/A | N/A |
FIELD NAME | BIT DEFINITION |
---|---|
VB_UV | Positive boost converter undervoltage detect interrupt |
1 – under-voltage on DCDC1 detected | |
0 – no fault | |
VDDH_UV | VDDH undervoltage detect interrupt |
1 – undervoltage on VDDH charge pump detected | |
0 – no fault | |
VN_UV | Inverting buck-boost converter undervoltage detect interrupt |
1 – undervoltage on DCDC2 detected | |
0 – no fault | |
VPOS_UV | VPOS undervoltage detect interrupt |
1 – undervoltage on LDO1(VPOS) detected | |
0 – no fault | |
VEE_UV | VEE undervoltage detect interrupt |
1 – undervoltage on VEE charge pump detected | |
0 – no fault | |
VCOMF | VCOM fault detection |
1 – fault on VCOM detected (VCOM is outside normal operating range) | |
0 – no fault | |
VNEG_UV | VNEG undervoltage detect interrupt |
1 – undervoltage on LDO2(VNEG) detected | |
0 – no fault | |
EOC | ADC end of conversion interrupt |
1 – ADC conversion is complete (temperature acquisition is complete) | |
0 – no significance |
DATA BIT | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
---|---|---|---|---|---|---|---|---|
FIELD NAME | VDDH_UP[1:0] | VPOS_UP[1:0] | VEE_UP[1:0] | VNEG_UP[1:0] | ||||
READ/WRITE | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
RESET VALUE | 1E2 | 1E2 | 1E2 | 0E2 | 0E2 | 1E2 | 0E2 | 0E2 |
FIELD NAME | BIT DEFINITION |
---|---|
VDDH_UP[1:0] | VDDH power-up order |
00 – power up on STROBE1 | |
01 – power up on STROBE2 | |
10 – power up on STROBE3 | |
11 – power up on STROBE4 | |
VPOS_UP[1:0] | VPOS power-up order |
00 – power up on STROBE1 | |
01 – power up on STROBE2 | |
10 – power up on STROBE3 | |
11 – power up on STROBE4 | |
VEE_UP[1:0] | VEE power-up order |
00 – power up on STROBE1 | |
01 – power up on STROBE2 | |
10 – power up on STROBE3 | |
11 – power up on STROBE4 | |
VNEG_UP[1:0] | VNEG power-up order |
00 – power up on STROBE1 | |
01 – power up on STROBE2 | |
10 – power up on STROBE3 | |
11 – power up on STROBE4 |
DATA BIT | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
---|---|---|---|---|---|---|---|---|
FIELD NAME | UDLY4[1:0] | UDLY3[1:0] | UDLY2[1:0] | UDLY1[1:0] | ||||
READ/WRITE | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
RESET VALUE | 0E2 | 1E2 | 0E2 | 1E2 | 0E2 | 1E2 | 0E2 | 1E2 |
FIELD NAME | BIT DEFINITION |
---|---|
UDLY4[1:0] | DLY4 delay time set; defines the delay time from STROBE3 to STROBE4 during power up. |
00 – 3 ms | |
01 – 6 ms | |
10 – 9 ms | |
11 – 12 ms | |
UDLY3[1:0] | DLY3 delay time set; defines the delay time from STROBE2 to STROBE3 during power up. |
00 – 3 ms | |
01 – 6 ms | |
10 – 9 ms | |
11 – 12 ms | |
UDLY2[1:0] | DLY2 delay time set; defines the delay time from STROBE1 to STROBE2 during power up. |
00 – 3 ms | |
01 – 6 ms | |
10 – 9 ms | |
11 – 12 ms | |
UDLY1[1:0] | DLY1 delay time set; defines the delay time from VN_PG high to STROBE1 during power up. |
00 – 3 ms | |
01 – 6 ms | |
10 – 9 ms | |
11 – 12 ms |
DATA BIT | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
---|---|---|---|---|---|---|---|---|
FIELD NAME | VDDH_DWN[1:0] | VPOS_DWN[1:0] | VEE_DWN[1:0] | VNEG_DWN[1:0] | ||||
READ/WRITE | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
RESET VALUE | 0E2 | 0E2 | 0E2 | 1E2 | 1E2 | 1E2 | 1E2 | 0E2 |
FIELD NAME | BIT DEFINITION |
---|---|
VDDH_DWN[1:0] | VDDH power-down order |
00 – power down on STROBE1 | |
01 – power down on STROBE2 | |
10 – power down on STROBE3 | |
11 – power down on STROBE4 | |
VPOS_DWN[1:0] | VPOS power-down order |
00 – power down on STROBE1 | |
01 – power down on STROBE2 | |
10 – power down on STROBE3 | |
11 – power down on STROBE4 | |
VEE_DWN[1:0] | VEE power-down order |
00 – power down on STROBE1 | |
01 – power down on STROBE2 | |
10 – power down on STROBE3 | |
11 – power down on STROBE4 | |
VNEG_DWN[1:0] | VNEG power-down order |
00 – power down on STROBE1 | |
01 – power down on STROBE2 | |
10 – power down on STROBE3 | |
11 – power down on STROBE4 |
DATA BIT | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
---|---|---|---|---|---|---|---|---|
FIELD NAME | DDLY4[1:0] | DDLY3[1:0] | DDLY2[1:0] | DDLY1 | DFCTR | |||
READ/WRITE | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
RESET VALUE | 1E2 | 1E2 | 1E2 | 0E2 | 0E2 | 0E2 | 0E2 | 0E2 |
FIELD NAME | BIT DEFINITION |
---|---|
DDLY4[1:0] | DLY4 delay time set; defines the delay time from STROBE3 to STROBE4 during power down. |
00 – 6 ms | |
01 – 12 ms | |
10 – 24 ms | |
11 – 48 ms | |
DDLY3[1:0] | DLY3 delay time set; defines the delay time from STROBE2 to STROBE3 during power down. |
00 – 6 ms | |
01 – 12 ms | |
10 – 24 ms | |
11 – 4 8ms | |
DDLY2[1:0] | DLY2 delay time set; defines the delay time from STROBE1 to STROBE2 during power down. |
00 – 6 ms | |
01 – 12 ms | |
10 – 24 ms | |
11 – 48 ms | |
DDLY1 | DLY2 delay time set; defines the delay time from WAKEUP low to STROBE1 during power down. |
0 – 3 ms | |
1 – 6 ms | |
DFCTR | At power-down delay time DLY2[1:0], DLY3[1:0], DLY4[1:0] are multiplied with DFCTR[1:0] |
0 – 1× | |
1 – 16× |
DATA BIT | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
---|---|---|---|---|---|---|---|---|
FIELD NAME | READ_THERM | not used | CONV_END | not used | not used | not used | DT[1:0] | |
READ/WRITE | R/W | R/W | R | R/W | R/W | R/W | R/W | R/W |
RESET VALUE | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 |
FIELD NAME | BIT DEFINITION |
---|---|
READ_THERM | Read thermistor value |
1 – initiates temperature acquisition | |
0 – no effect | |
NOTE: Bit is self-cleared after acquisition is completed | |
not used | N/A |
CONV_END | ADC conversion done flag |
1 – conversion is finished | |
0 – conversion is not finished | |
not used | N/A |
not used | N/A |
DT[1:0] | Panel temperature-change interrupt threshold |
00 – 2°C | |
01 – 3°C | |
10 – 4°C | |
11 – 5°C | |
DTX interrupt is issued when difference between most recent temperature reading and baseline temperature is equal to or greater than threshold value. See Hot, Cold, and Temperature-Change Interrupts for details. |
DATA BIT | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
---|---|---|---|---|---|---|---|---|
FIELD NAME | TMST_COLD[3:0] | TMST_HOT[3:0] | ||||||
READ/WRITE | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
RESET VALUE | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
FIELD NAME | BIT DEFINITION |
---|---|
TMST_COLD [3:0] | Thermistor COLD threshold |
0000 – -7°C | |
0001 – -6°C | |
0010 – -5°C | |
0011 – -4°C | |
0100 – -3°C | |
0101 – -2°C | |
0110 – -1°C | |
0111 – 0°C | |
1000 – 1°C | |
1001 – 2°C | |
1010 – 3°C | |
1011 – 4°C | |
1100 – 5°C | |
1101 – 6°C | |
1110 – 7°C | |
1111 – 8°C | |
NOTE: An interrupt is issued when thermistor temperature is equal or less than COLD threshold | |
TMST_HOT [3:0] | Thermistor HOT threshold |
0000 – 42°C | |
0001 – 43°C | |
0010 – 44°C | |
0011 – 45°C | |
0100 – 46°C | |
0101 – 47°C | |
0110 – 48°C | |
0111 – 49°C | |
1000 – 50°C | |
1001 – 51°C | |
1010 – 52°C | |
1011 – 53°C | |
1100 – 54°C | |
1101 – 55°C | |
1110 – 56°C | |
1111 – 57°C | |
NOTE: An interrupt is issued when thermistor temperature is equal or greater than HOT threshold |
DATA BIT | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
---|---|---|---|---|---|---|---|---|
FIELD NAME | VB_PG | VDDH_PG | VN_PG | VPOS_PG | VEE_PG | not used | VNEG_PG | not used |
READ/WRITE | R | R | R | R | R | R | R | R |
RESET VALUE | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
FIELD NAME | BIT DEFINITION(1) |
---|---|
VB_PG | Positive boost converter power good |
1 – DCDC1 is in regulation | |
0 – DCDC1 is not in regulation or turned off | |
VDDH_PG | VDDH power good |
1 – VDDH charge pump is in regulation | |
0 – VDDH charge pump is not in regulation or turned off | |
VN_PG | Inverting buck-boost power good |
1 – DCDC2 is in regulation | |
0 – DCDC2 is not in regulation or turned off | |
VPOS_PG | VPOS power good |
1 – LDO1(VPOS) is in regulation | |
0 – LDO1(VPOS) is not in regulation or turned off | |
VEE_PG | VEE power good |
1 – VEE charge pump is in regulation | |
0 – VEE charge pump is not in regulation or turned off | |
not used | N/A |
VNEG_PG | VNEG power good |
1 – LDO2(VNEG) is in regulation | |
0 – LDO2(VNEG) is not in regulation or turned off | |
not used | N/A |
DATA BIT | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
---|---|---|---|---|---|---|---|---|
FIELD NAME | REVID[7:0] | |||||||
READ/WRITE | R | R | R | R | R | R | R | R |
RESET VALUE | 0 | 1 | 0 | 0 | 0E2 | 1E2 | 0E2 | 1E2 |
FIELD NAME | BIT DEFINITION |
---|---|
REVID[7:6] | MJREV |
REVID[5:4] | MNREV |
REVID[3:0] | VERSION |
REVID [7:0] | 0100 0101 - TPS65186 1p0 |
0101 0101 – TPS65186 1p1 | |
0110 0101 – TPS65186 1p2 |