SLVSB04A
July 2011 – August 2015
TPS65186
PRODUCTION DATA.
1
Features
2
Applications
3
Description
4
Revision History
5
Description (continued)
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Timing Requirements: Data Transmission
7.7
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Wake-Up and Power-Up Sequencing
8.3.2
Dependencies Between Rails
8.3.3
Soft Start
8.3.4
VPOS/VNEG Supply Tracking
8.3.5
V3P3 Power Switch
8.3.6
VCOM Adjustment
8.3.6.1
Kick-Back Voltage Measurement
8.3.6.2
Storing the VCOM Power-Up Default Value in Memory
8.3.7
Fault Handling and Recovery
8.3.8
Power Good Pin
8.3.9
Interrupt Pin
8.3.10
Panel Temperature Monitoring
8.3.10.1
NTC Bias Circuit
8.3.10.2
Hot, Cold, and Temperature-Change Interrupts
8.3.10.3
Typical Application of the Temperature Monitor
8.4
Device Functional Modes
8.4.1
SLEEP
8.4.2
STANDBY
8.4.3
ACTIVE
8.4.4
Mode Transitions
8.4.4.1
SLEEP → ACTIVE
8.4.4.2
SLEEP → STANDBY
8.4.4.3
STANDBY → ACTIVE
8.4.4.4
ACTIVE → STANDBY
8.4.4.5
STANDBY → SLEEP
8.4.4.6
ACTIVE → SLEEP
8.5
Programming
8.5.1
I2C Bus Operation
8.6
Register Maps
8.6.1
Thermistor Readout (TMST_VALUE)
8.6.2
Enable (ENABLE)
8.6.3
Voltage Adjustment Register (VADJ)
8.6.4
VCOM 1 (VCOM1)
8.6.5
VCOM 2 (VCOM2)
8.6.6
Interrupt Enable 1 (INT_EN1)
8.6.7
Interrupt Enable 2 (INT_EN2)
8.6.8
Interrupt 1 (INT1)
8.6.9
Interrupt 2 (INT2)
8.6.10
Power Up Sequence Register 0 (UPSEQ0)
8.6.11
Power Up Sequence Register 1 (UPSEQ1)
8.6.12
Power Down Sequence Register 0 (DWNSEQ0)
8.6.13
Power Down Sequence Register 1 (DWNSEQ1)
8.6.14
Thermistor Register 1 (TMST1)
8.6.15
Thermistor Register 2 (TMST2)
8.6.16
Power Good Status (PG)
8.6.17
Revision and Version Control (REVID)
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.3
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Device Support
12.1.1
Third-Party Products Disclaimer
12.2
Community Resources
12.3
Trademarks
12.4
Electrostatic Discharge Caution
12.5
Glossary
13
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RGZ|48
MPQF123F
Thermal pad, mechanical data (Package|Pins)
RGZ|48
QFND014T
Orderable Information
slvsb04a_oa
slvsb04a_pm
11 Layout
11.1 Layout Guidelines
PBKG (Die substrate) must connect to VN (–16 V) with short, wide trace. Wide copper trace will improve heat dissipation.
PowerPad is internally connected to PBKG and must not be connected to ground, but connected to VN with a short wide copper trace.
Inductor traces must be kept on the PCB top layer free of any vias.
Feedback traces must be routed away from any potential noise source to avoid coupling.
Output caps must be placed immediately at output pin.
Vin pins must be bypassed to ground with low ESR ceramic bypass capacitors.
11.2 Layout Example
Figure 33. Layout Diagram