SLVSBB0D April   2012  – February 2018 TPS65197

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Sequencing
      2. 7.3.2 Power Up
      3. 7.3.3 Power Down
      4. 7.3.4 Disabling the Discharge Function
      5. 7.3.5 Undervoltage Lockout
      6. 7.3.6 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Output Clock Behavior
      2. 7.4.2 Charge-Sharing Methods TPS65197
      3. 7.4.3 Charge-Sharing Methods TPS65197B
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.1 Layout Guidelines

Proper PCB layout is essential for achieving the expected performance and a low device temperature. The following points should be considered.

  • Place the supply decoupling capacitors as close as possible to device terminals VGH and VGL1.
  • Use wide traces to route power from the bias IC to the device to avoid voltage drops. The device is able to sink and source high peak currents up to 1 A. If wide traces are not possible, place additional 1-µF capacitors of at least 0805 size close to the supply decoupling capacitors.
  • The output channel traces should be kept as short as possible to reduce EMI emissions, and not too thin to minimize stray inductances producing voltage overshoots at the panel, because high peak currents up to 1 A can flow.
  • The thermal pad must be connected by many vias to a large copper area on a VGL1 potential, to be used as a heat sink. Use a copper area of at least 10 cm2. The bigger the copper area, the cooler the device temperature. On a multilayer board, use the copper areas of as many layers as possible to maximize the heat sink.
  • Output resistors for clock channels 1 to 6 can be used to reduce EMI emissions and device temperature if necessary. They generate heat and should therefore not be placed close to the device.