SLVSBB0D April   2012  – February 2018 TPS65197

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Sequencing
      2. 7.3.2 Power Up
      3. 7.3.3 Power Down
      4. 7.3.4 Disabling the Discharge Function
      5. 7.3.5 Undervoltage Lockout
      6. 7.3.6 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Output Clock Behavior
      2. 7.4.2 Charge-Sharing Methods TPS65197
      3. 7.4.3 Charge-Sharing Methods TPS65197B
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.1 Output Clock Behavior

The STV and RESET channels always follow their inputs while the clocks 1 to 6 behave different for TPS65197 and TPS65197B.

TPS65197:

At startup the output signals CLKOUT1 to CLKOUT6 are forced low (VGL1) until the first rising edge of CLKOUT1 releases all clocks. Every rising edge of STVIN stops the Charge-Sharing and resets the output signals CLKOUT1 to CLKOUT6 (that is, forced low) until the next rising edge of CLKIN1 after which the clock outputs follow their inputs again. The rising edge of CLKIN1 should occur not sooner than 50 ns after the rising edge of STVIN. This logic ensures a proper reset and a clean start every frame.

TPS65197B:

The TPS65197B does not have the reset logic as TPS65197 and all outputs always follow their input signals (also at startup). If Charge-Sharing is activated every rising edge of STVIN stops the Charge-Sharing and the output signals CLKOUT1 to CLKOUT6 follow their input signals. The next Charge-Sharing event should not occur sooner than 50 ns after the rising edge of STVIN.