7.3.2.1 Undervoltage Lockout

An undervoltage lockout circuit prevents operation of the WLED driver at input voltages (CSOUT pin) below 2.2 V. When the input voltage is below the under voltage threshold, the driver is shutdown and the internal switch FET is turned off. If the input voltage rises by 70 mV above the undervoltage lockout hysteresis, the WLED driver restarts. An internal thermal shutdown turns off the device when the typical junction temperature of 165°C is exceeded. The device is released from shutdown automatically when the junction temperature decreases by 10°C.

7.3.2.2 Shutdown

To minimize current consumption, the WLED driver is shutdown when the WLED_EN bit is low and the CTRL pin is pulled low for more than 2.5 ms. Although the internal FET does not switch in shutdown, there is still a DC current path between the input and the LEDs through the inductor and Schottky diode. The minimum forward voltage of the LED array must exceed the maximum input voltage to ensure that the LEDs remain off in shutdown. However, in the typical application with two or more LEDs, the forward voltage is large enough to reverse bias the Schottky and keep leakage current low.

7.3.2.3 Soft-Start Circuit

Soft-start circuitry is integrated into the WLED driver to avoid a high inrush current during start-up. After the device is enabled, the voltage at FB pin ramps up to the reference voltage in 32 steps, each step takes 213 µs. This ensures that the output voltage rises slowly to reduce the input current. Additionally, for the first 5 ms after the COMP voltage ramps, the current limit of the switch is set to half of the normal current limit specification. During this period, the input current is kept below 400 mA (typical).

7.3.2.4 Open LED Protection

Open LED protection circuitry prevents IC damage as the result of white LED disconnection. The TPS65200 monitors the voltage at the SWL pin during each switching cycle. The circuitry turns off the switch FET and shuts down the WLED driver as soon as the SWL voltage exceeds the V_OVP threshold for eight clock cycles. As a result, the output voltage falls to the level of the input supply. The WLED driver remains in shutdown mode until it is enabled by toggling the CTRL pin or the WLED_EN bit of the CTRL register.

7.3.2.5 Current Program

The FB voltage is regulated to a low 200-mV reference voltage. The LED current is programmed externally using a current-sense resistor in series with the LED string. The value of the RSET is calculated using Equation 1.

Equation 1.

where

• I_LED = output current of LEDs
• V_FB = regulated voltage of FB
• R_SET = current sense resistor

The output current tolerance depends on the FB accuracy and the current sensor resistor accuracy.

7.3.2.6 Brightness Dimming

The TPS65200 offers two methods of LED brightness dimming. When the CTRL pin is constantly high, the FB voltage is regulated to the value set in the WLED register which ranges from 0 mV to 200 mV and is divided into 32 steps. For applications requiring higher dimming resolution, a PWM signal can be applied to the CTRL pin to reduce this regulation voltage and dim LED brightness. The relationship between the duty cycle and FB voltage is given by Equation 2.

Equation 2.

where

• Duty = duty cycle of the PWM signal
• VFB[4:0] = internal reference voltage, default = 200 mV

The IC chops up the internal reference voltage at the duty cycle of the PWM signal and filters it by an internal low pass filter. The output of the filter is connected to the error amplifier as the reference voltage for the FB pin regulation. Therefore, although a PWM signal is used for brightness dimming, only the WLED DC current is modulated, which is often referred to as analog dimming. This eliminates the audible noise which often occurs when the LED current is pulsed in replica of the frequency and duty cycle of PWM control. The regulation voltage itself is independent of the PWM logic voltage level which often has large variations.

Figure 38. WLED Analog Dimming Circuit

7.3.2.7 Inductor Overcurrent Protection

The overcurrent limit in the boost converter limits the maximum input current and thus maximum input power for a given input voltage. Maximum output power is less than maximum input power due to power conversion losses. Therefore, the current limit setting, input voltage, output voltage and efficiency can all change maximum current output. The current limit clamps the peak inductor current and the maximum DC output current equals the current limit minus half of the peak-peak current ripple. The ripple current is a function of switching frequency, inductor value and duty cycle. Equation 3 through Equation 5 are used to determine the maximum output current.

Equation 3.

where

• D = duty cycle of the boost converter
• V_IN = Input voltage
• V_OUT = Output voltage of the boost converter. It is equal to the sum of VFB and the voltage drop across LEDs.

Equation 4.

where

• I_PP = inductor peak to peak ripple
• L = inductor value
• f_s = switching frequency

Equation 5.

where

• I_OUT(MAX) = maximum output current of the boost converter
• I_LIM = overcurrent limit
• η = efficiency

For instance, for V_IN = 3 V, 7 LEDs output equivalent to V_OUT of 23 V, an inductor value of 22 µH, a current limit of 700 mA, and an efficiency of 85%, the maximum output current is ~65 mA.

7.4.1.1 Input Current Limiting and D+/D- Detection

By default the VBUS input current limit is set to 500 mA. When VBUS is asserted the TPS65200 performs a charger source identification to determine if it is connected to a USB port or dedicated charger. This detection is performed 200 ms after VBUS is asserted to ensure the USB plug has been fully inserted before identification is performed. If a dedicated charger is detected the input current limit is increased to 975 mA, otherwise the current limit remains at 500 mA, unless changed by the user.

Automatic detection is performed only if VIO is below 0.6 V to avoid interfering with the USB transceiver which may also perform D+/D- detection when the system is running normally. However, D+/D- can be initiated at any time by the host by setting the DPDM_EN bit in the CONTROL register to 1. After detection is complete the DPDM_EN bit is automatically reset to 0 and the detection circuitry is disconnected from the DP DM pins to avoid interference with USB data transfer.

The input current limit can also be set through the I²C interface to 100 mA, 500 mA, 975 mA, or no limit by writing to the CONFIG_B register. The effective current limit will be the higher of the D+D- detection result and the IIN_LIMIT[1:0] setting in CONFIG_A register. Whenever VBUS drops below the UVLO threshold IIN_LIMIT[1:0] is reset to 100-mA setting to avoid excessive current draw from an unknown USB port.

Once the input current reaches the input current limiting threshold, the charge current is reduced to keep the input current from exceeding the programmed threshold. The host can choose to ignore the D+D- detection result by setting the LMTSEL bit of the CONFIG_A register to 1.

Figure 42. Adaptor Identification Algorithm and Block Diagram

7.4.1.2 Bad Adaptor Detection/Rejection (CHBADI)

At the beginning of the charge cycle, the IC will perform the bad adaptor detection by applying a current sink to VBUS. If V_VBUS is higher than V_IN(MIN) for 30 ms, the adaptor is good and the charge process will begin. However, if V_VBUS drops below V_IN(MIN), a bad adaptor is detected. Then, the IC will disable the current sink, issue an interrupt and set the CHBADI interrupt in the INT2 register. After a delay of TINT (2s), the IC will repeat the adaptor detection process, as shown in Figure 44.

If the battery voltage is high (> 3.8 V), it is possible that the input voltage drops below the battery voltage during adaptor rejection test. In this case, the reverse protection will kick-in and disable the charger. Also note that the 30-mA current sink is turned on for 30 ms only. If the input capacitance is > 500 µF (not recommended), the adaptor may be accepted although it is not capable of providing 30-mA of current. In these cases, the VDPPM loop will limit the charging current to maintain the input voltage.

Figure 43. Bad Adaptor Detection Circuit

Figure 44. Bad Adaptor Detection Flow-Chart

7.4.1.3 Input Current Limiting at Start-Up

The LOW_CHG bit is automatically set when VBUS is asserted to limit the charge current to 150 mA. This ensures that a battery cannot be charged with high currents without host control.

7.4.1.4 Charge Profile

In charge mode, TPS65200 has five control loops to regulate input voltage, input current, charge current, charge voltage, and device junction temperature. During the charging process, all five loops are enabled and the one that is dominant will take over the control. The TPS65200 supports a precision Li-ion or Li-polymer charging system for single-cell applications. Figure 46 indicates a typical charge profile without input current regulation loop and it is similar to the traditional CC/CV charge curve, while Figure 47 shows a typical charge profile when input current limiting loop is dominant during the constant current mode, and in this case the charge current is higher than the input current so the charge process is faster than the linear chargers. For TPS65200, the input current limits, the charge current, termination current, and charge voltage are all programmable using I²C interface.

7.4.1.5 Precharge to Fast Charge Threshold (VSHORT)

A deeply discharged battery (V_BAT < V_SHORT) is charged with a constant current of I_SHORT (typically 30 mA) until the voltage recovers to > V_SHORT at which point fast charging begins. The pre-charge to fast-charge threshold has a default value of 2.1 V and can be adjusted by connecting a resistor from the VSHRT pin to ground. An internal current source forces a 10-µA current into the resistor and the resulting voltage is compared to half the battery voltage to determine if the battery is deeply discharged or shorted. Therefore the voltage on the VSHRT pin equals half of V_SHORT threshold. For example a 100-kΩ resistor connected from VSHRT to GND results in a 2-V precharge to fast charge transition point. If the VSHRT pin is left floating or is shorted to the VDD pin, an internal reference voltage of 1.05 V is used resulting in a 2.1-V pre-charge to fast-charge threshold.

Figure 45. Precharge to Fast-Charge Transition Threshold (VSHORT)

Figure 46. Typical Charging Profile of TPS65200 Without Input Current Limit

Figure 47. Typical Charging Profile of TPS65200 With Input Current Limit

7.4.1.6 PWM Controller in Charge Mode

The TPS65200 provides an integrated, fixed 3-MHz frequency voltage-mode controller with feed-forward function to regulate charge current or voltage. This type of controller is used to help improve line transient response, thereby simplifying the compensation network used for both continuous and discontinuous current conduction operation. The voltage and current loops are internally compensated using a Type-III compensation scheme that provides enough phase margin for stable operation, allowing the use of small ceramic capacitors with very low ESR. There is a 0.5-V offset on the bottom of the PWM ramp to allow the device to operate between 0% to 99.5% duty cycles.

The TPS65200 has two back-to-back common-drain N-channel MOSFETs at the high side and one N-channel MOSFET at the low side. An input N-MOSFET (Q1) prevents battery discharge when VBUS is lower than V_CSOUT. The second high-side N-MOSFET (Q2) behaves as the switching control switch. A charge pump circuit is used to provide gate drive for Q1, while a boot strap circuit with external boot-strap capacitor is used to boost up the gate drive voltage for Q2.

Cycle-by-cycle current limit is sensed through the internal sense MOSFETs for Q2 and Q3. The threshold for Q2 is set to a nominal 1.9-A peak current. The low-side MOSFET (Q3) also has a current limit that decides if the PWM controller will operate in synchronous or non-synchronous mode. This threshold is set to 100mA and it turns off the low-side N-channel MOSFET (Q3) before the current reverses, preventing the battery from discharging. Synchronous operation is used when the current of the low-side MOSFET is greater than 100 mA to minimize power losses.

7.4.1.7 Battery Charging Process

During precharge phase, while the battery voltage is below the V_SHORT threshold, the TPS65200 applies a short-circuit current, I_SHORT, to the battery. When the battery voltage is above V_SHORT and below V_OREG, the charge current ramps up to fast charge current, I_OCHARGE, or a charge current that corresponds to the input current of I_{IN_LIMIT}. The slew rate for fast charge current is controlled to minimize the current and voltage over-shoot during transient. Both the input current limit (default at 100 mA), I_{IN_LIMIT}, and fast charge current, I_OCHARGE, can be set by the host. Once the battery voltage is close to the regulation voltage, V_OREG, the charge current is tapered down as shown in Figure 46. The voltage regulation feedback occurs by monitoring the battery-pack voltage between the CSOUT and PGND pins. TPS65200 is a fixed single-cell voltage version, with adjustable regulation voltage (3.5 V to 4.44 V) programmed through I²C interface.

The TPS65200 monitors the charging current during the voltage regulation phase. When the termination threshold, I_TERM, is detected and the battery voltage is above the recharge threshold, the TPS65200 terminates charge. The termination current level is programmable and charge termination is disabled by default. To enable the charge current termination, the host can set the charge termination bit TERM_EN of CONFIG_C register to 1. Refer to I²C section for details.

A new charge cycle is initiated when one of the following events occur:

• VBUS is power-cycled.
• CH_EN[1:0] = 11b and the battery voltage drops below the recharge threshold (TERM_EN = 1).
• The RESET bit is set (host controlled).
• The device is in CHARGE DONE state (see Figure 40) and the TERM_EN bit is set from 1 to 0.

7.4.1.8 Thermal Regulation and Protection

During the charging process, to prevent overheating of the chip, TPS65200 monitors the junction temperature, T_J, of the die and begins to taper down the charge current once T_J reaches the thermal regulation threshold, T_CF. The charge current will be reduced to zero when the junction temperature increases about 10°C above T_CF. At any state, if T_J exceeds T_SHTDWN, TPS65200 will suspend charging and enter HiZ state. Charging will resume after T_J falls 10°C below T_SHTDWN.

7.4.1.9 Safety Timer in Charge and Boost Mode (CH32MI, BST32SI)

The TPS65200 charger hosts a safety timer that stops any boost or charging action if host control is lost. The timer is started when the CH_EN[1:0] bits are set to anything different from 00 and is continuously reset by any valid I²C command. If the timer exceeds 32 s and boost mode is enabled (CH_EN[1:0] = 01b), the boost is disabled, CH_EN[1:0] is set to 00b, boost time-out fault is indicated in the INT2 register, and an interrupt is issued. Similarly, once the timer exceeds 32 minutes and the charger is enabled (CH_EN[1:0] = 10b or 11b), the charger is disabled, CH_EN[1:0] is set to 00b, charger time-out fault is indicated in INT2 register and an interrupt is issued. Time-out faults affect CH_EN[1:0] bits only and not charger parameters. The safety timer flow chart is shown in Figure 48.

Figure 48. Timer Flow Chart for TPS65200 Charger

7.4.1.10 Input Voltage Protection in Charge Mode

7.4.1.11 Battery Protection in Charge Mode

7.4.1.12 Charge Status Output, STAT Pin

The STAT pin is used to indicate charging status of the IC and its behavior can be controlled by setting the STAT_EN bits of the CONTROL register. In AUTO mode, STAT is pulled low during charging and is high-impedance otherwise. STAT pin can also be forced low or to Hi-Z state by setting the STAT_EN bits accordingly. The STAT pin has enough pulldown strength to drive a LED and can be used for visual charge status indication.

7.4.2.1 PWM Controller in Boost Mode

Similar to charge mode operation, in boost mode, the TPS65200 provides an integrated, fixed 3-MHz frequency voltage-mode controller to regulate output voltage at PMID pin (V_PMID). The voltage control loop is internally compensated using a Type-III compensation scheme that provides enough phase margin for stable operation with a wide load range and battery voltage range.

In boost mode, the input N-MOSFET (Q1) prevents battery discharge when VBUS pin is over loaded. Cycle-by-cycle current limit is sensed through the internal sense MOSFET for Q3. The threshold for Q3 is set to a nominal 1.0-A peak current. The upper-side MOSFET (Q2) also has a current limit that decides if the PWM controller will operate in synchronous or non-synchronous mode. This threshold is set to 75 mA and it turns off the high-side N-channel MOSFET (Q2) before the current reverses, preventing the battery from charging. Synchronous operation is used when the current of the high-side MOSFET is greater than 75 mA to minimize power losses.

7.4.2.2 Boost Start Up

To prevent the inductor saturation and limit the inrush current, a soft-start control is applied during the boost start up.

7.4.2.3 PFM Mode at Light Load

In boost mode, TPS65200 will operate in pulse skipping mode (PFM mode) to reduce the power loss and improve the converter efficiency at light load condition. During boosting, the PWM converter is turned off once the inductor current is less than 75 mA; and the PWM is turned back on only when the voltage at PMID pin drops to about 99.5% of the rated output voltage. A unique pre-set circuit is used to make the smooth transition between PWM and PFM mode.

7.4.2.4 Safety Timer in Boost Mode (BST32SI)

At the beginning of boost operation, the TPS65200 starts a 32-second timer that is reset by the host through any valid I²C transaction to the IC. Once the 32-second timer expires, TPS65200 will turn off the boost converter, issue an interrupt, set the BST32SI bit in the INT3 register, and return to Hi-Z mode. Fault condition is cleared by POR or reading the INT3 register.

7.4.2.5 Protection in Boost Mode