SLDS187A October   2018  – December 2019 TPS65216

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Simplified Schematic
  2. 2 Revision History
  3. 3 Pin Configuration and Functions
    1. 3.1 Pin Functions
      1.      Pin Functions
  4. 4 Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Thermal Information
    5. 4.5 Electrical Characteristics
    6. 4.6 Timing Requirements
    7. 4.7 Typical Characteristics
  5. 5 Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1 Wake-Up and Power-Up and Power-Down Sequencing
        1. 5.3.1.1  Power-Up Sequencing
        2. 5.3.1.2  Power-Down Sequencing
        3. 5.3.1.3  Strobe 1 and Strobe 2
        4. 5.3.1.4  Supply Voltage Supervisor and Power-Good (PGOOD)
        5. 5.3.1.5  Internal LDO (INT_LDO)
        6. 5.3.1.6  Current Limited Load Switch
        7. 5.3.1.7  LDO1
        8. 5.3.1.8  UVLO
        9. 5.3.1.9  Power-Fail Comparator
        10. 5.3.1.10 DCDC3 and DCDC4 Power-Up Default Selection
        11. 5.3.1.11 I/O Configuration
          1. 5.3.1.11.1 Using GPIO2 as Reset Signal to DCDC1 and DCDC2
        12. 5.3.1.12 Push Button Input (PB)
          1. 5.3.1.12.1 Signaling PB-Low Event on the nWAKEUP Pin
          2. 5.3.1.12.2 Push Button Reset
        13. 5.3.1.13 AC_DET Input (AC_DET)
        14. 5.3.1.14 Interrupt Pin (INT)
        15. 5.3.1.15 I2C Bus Operation
    4. 5.4 Device Functional Modes
      1. 5.4.1 Modes of Operation
      2. 5.4.2 OFF
      3. 5.4.3 ACTIVE
      4. 5.4.4 SUSPEND
      5. 5.4.5 RESET
    5. 5.5 Register Maps
      1. 5.5.1 Password Protection
      2. 5.5.2 FLAG Register
      3. 5.5.3 TPS65216 Registers
        1. 5.5.3.1  CHIPID Register (subaddress = 0x00) [reset = 0x05]
          1. Table 5-7 CHIPID Register Field Descriptions
        2. 5.5.3.2  INT1 Register (subaddress = 0x01) [reset = 0x00]
          1. Table 5-8 INT1 Register Field Descriptions
        3. 5.5.3.3  INT2 Register (subaddress = 0x02) [reset = 0x00]
          1. Table 5-9 INT2 Register Field Descriptions
        4. 5.5.3.4  INT_MASK1 Register (subaddress = 0x03) [reset = 0x00]
          1. Table 5-10 INT_MASK1 Register Field Descriptions
        5. 5.5.3.5  INT_MASK2 Register (subaddress = 0x04) [reset = 0x00]
          1. Table 5-11 INT_MASK2 Register Field Descriptions
        6. 5.5.3.6  STATUS Register (subaddress = 0x05) [reset = 00XXXXXXb]
          1. Table 5-12 STATUS Register Field Descriptions
        7. 5.5.3.7  CONTROL Register (subaddress = 0x06) [reset = 0x00]
          1. Table 5-13 CONTROL Register Field Descriptions
        8. 5.5.3.8  FLAG Register (subaddress = 0x07) [reset = 0x00]
          1. Table 5-14 FLAG Register Field Descriptions
        9. 5.5.3.9  PASSWORD Register (subaddress = 0x10) [reset = 0x00]
          1. Table 5-15 PASSWORD Register Field Descriptions
        10. 5.5.3.10 ENABLE1 Register (subaddress = 0x11) [reset = 0x00]
          1. Table 5-16 ENABLE1 Register Field Descriptions
        11. 5.5.3.11 ENABLE2 Register (subaddress = 0x12) [reset = 0x00]
          1. Table 5-17 ENABLE2 Register Field Descriptions
        12. 5.5.3.12 CONFIG1 Register (subaddress = 0x13) [reset = 0x4C]
          1. Table 5-18 CONFIG1 Register Field Descriptions
        13. 5.5.3.13 CONFIG2 Register (subaddress = 0x14) [reset = 0xC0]
          1. Table 5-19 CONFIG2 Register Field Descriptions
        14. 5.5.3.14 CONFIG3 Register (subaddress = 0x15) [reset = 0x0]
          1. Table 5-20 CONFIG3 Register Field Descriptions
        15. 5.5.3.15 DCDC1 Register (offset = 0x16) [reset = 0x99]
          1. Table 5-21 DCDC1 Register Field Descriptions
        16. 5.5.3.16 DCDC2 Register (subaddress = 0x17) [reset = 0x99]
          1. Table 5-22 DCDC2 Register Field Descriptions
        17. 5.5.3.17 DCDC3 Register (subaddress = 0x18) [reset = 0x8C]
          1. Table 5-23 DCDC3 Register Field Descriptions
        18. 5.5.3.18 DCDC4 Register (subaddress = 0x19) [reset = 0xB2]
          1. Table 5-24 DCDC4 Register Field Descriptions
        19. 5.5.3.19 SLEW Register (subaddress = 0x1A) [reset = 0x06]
          1. Table 5-25 SLEW Register Field Descriptions
        20. 5.5.3.20 LDO1 Register (subaddress = 0x1B) [reset = 0x1F]
          1. Table 5-26 LDO1 Register Field Descriptions
        21. 5.5.3.21 SEQ1 Register (subaddress = 0x20) [reset = 0x00]
          1. Table 5-27 SEQ1 Register Field Descriptions
        22. 5.5.3.22 SEQ2 Register (subaddress = 0x21) [reset = 0x00]
          1. Table 5-28 SEQ2 Register Field Descriptions
        23. 5.5.3.23 SEQ3 Register (subaddress = 0x22) [reset = 0x98]
          1. Table 5-29 SEQ3 Register Field Descriptions
        24. 5.5.3.24 SEQ4 Register (subaddress = 0x23) [reset = 0x75]
          1. Table 5-30 SEQ4 Register Field Descriptions
        25. 5.5.3.25 SEQ5 Register (subaddress = 0x24) [reset = 0x12]
          1. Table 5-31 SEQ5 Register Field Descriptions
        26. 5.5.3.26 SEQ6 Register (subaddress = 0x25) [reset = 0x63]
          1. Table 5-32 SEQ6 Register Field Descriptions
        27. 5.5.3.27 SEQ7 Register (subaddress = 0x26) [reset = 0x03]
          1. Table 5-33 SEQ7 Register Field Descriptions
  6. 6 Application and Implementation
    1. 6.1 Application Information
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
        1. 6.2.2.1 Output Filter Design
        2. 6.2.2.2 Inductor Selection for Buck Converters
        3. 6.2.2.3 Output Capacitor Selection
      3. 6.2.3 Application Curves
  7. 7 Power Supply Recommendations
  8. 8 Layout
    1. 8.1 Layout Guidelines
    2. 8.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Package Option Addendum
      1. 10.1.1 Packaging Information
      2. 10.1.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.4.3 ACTIVE

This is the typical mode of operation when the system is up and running. All DCDC converters, LDOs, and load switch are operational and can be controlled through the I2C interface. After a wake-up event, the PMIC enables all rails controlled by the sequencer and pulls the nWAKEUP pin low to signal the event to the host processor. The device only enters ACTIVE state if the host asserts the PWR_EN pin within 20 s after the wake-up event. Otherwise it will enter OFF state. The nWAKEUP pin returns to HiZ mode after the PWR_EN pin is asserted. ACTIVE state can also be directly entered from SUSPEND state by pulling the PWR_EN pin high. See SUSPEND state description for details. To exit ACTIVE mode, the PWR_EN pin must be pulled low.