SLVSB64I November   2011  – March 2018 TPS65217

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Application Diagram
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Wake-Up and Power-Up Sequencing
        1. 8.3.1.1 Power-Up Sequencing
        2. 8.3.1.2 Power-Down Sequencing
        3. 8.3.1.3 Special Strobes (STROBE 14 and 15)
      2. 8.3.2  Power Good
        1. 8.3.2.1 LDO1, LDO2 Power-Good (LDO_PGOOD)
        2. 8.3.2.2 Primary Power-Good (PGOOD)
        3. 8.3.2.3 Load Switch PGOOD
      3. 8.3.3  Push-Button Monitor (PB_IN)
      4. 8.3.4  nWAKEUP Pin (nWAKEUP)
      5. 8.3.5  Power Enable Pin (PWR_EN)
      6. 8.3.6  Reset Pin (nRESET)
      7. 8.3.7  Interrupt Pin (nINT)
      8. 8.3.8  Analog Multiplexer
      9. 8.3.9  Battery Charger and Power Path
        1. 8.3.9.1 Shorted or Absent Battery (VBAT < 1.5 V)
        2. 8.3.9.2 Dead Battery (1.5 V < VBAT < VUVLO)
        3. 8.3.9.3 Good Battery (VBAT > VUVLO)
        4. 8.3.9.4 AC and USB Input Discharge
      10. 8.3.10 Battery Charging
      11. 8.3.11 Precharge
      12. 8.3.12 Charge Termination
      13. 8.3.13 Battery Detection and Recharge
      14. 8.3.14 Safety Timer
        1. 8.3.14.1 Dynamic Timer Function
        2. 8.3.14.2 Timer Fault
      15. 8.3.15 Battery-Pack Temperature Monitoring
      16. 8.3.16 DC/DC Converters
        1. 8.3.16.1 Operation
        2. 8.3.16.2 Output Voltage Setting
        3. 8.3.16.3 Power-Save Mode and Pulse-Frequency Modulation (PFM)
        4. 8.3.16.4 Dynamic Voltage Positioning
        5. 8.3.16.5 100% Duty-Cycle Low-Dropout Operation
        6. 8.3.16.6 Short-Circuit Protection
        7. 8.3.16.7 Soft Start
      17. 8.3.17 Standby LDO Regulators (LDO1, LDO2)
      18. 8.3.18 Load Switches or LDO Regulators (LS1 or LDO3, LS2 or LDO4)
      19. 8.3.19 White LED Driver
    4. 8.4 Device Functional Modes
      1. 8.4.1 PMIC States
        1. 8.4.1.1 OFF State
        2. 8.4.1.2 ACTIVE State
        3. 8.4.1.3 SLEEP State
        4. 8.4.1.4 RESET State
    5. 8.5 Programming
      1. 8.5.1 I2C Bus Operation
      2. 8.5.2 Password Protection
        1. 8.5.2.1 Level1 Protection
        2. 8.5.2.2 Level2 Protection
      3. 8.5.3 Resetting of Registers to Default Values
    6. 8.6 Register Maps
      1. 8.6.1  Register Address Map
      2. 8.6.2  Chip ID Register (CHIPID) (Address = 0x00) [reset = X]
        1. Table 2. CHIPID Register Field Descriptions
      3. 8.6.3  Power Path Control Register (PPATH) (Address = 0x01) [reset = 0x3D]
        1. Table 3. PPATH Register Field Descriptions
      4. 8.6.4  Interrupt Register (INT) (Address = 0x02) [reset = 0x80]
        1. Table 4. INT Register Field Descriptions
      5. 8.6.5  Charger Configuration Register 0 (CHGCONFIG0) (Address = 0x03) [reset = 0x00]
        1. Table 5. CHGCONFIG0 Register Field Descriptions
      6. 8.6.6  Charger Configuration Register 1 (CHGCONFIG1) (Address = 0x04) [reset = 0xB1]
        1. Table 6. CHGCONFIG1 Register Field Descriptions
      7. 8.6.7  Charger Configuration Register 2 (CHGCONFIG2) (Address = 0x05) [reset = 0x80]
        1. Table 7. CHGCONFIG2 Register Field Descriptions
      8. 8.6.8  Charger Configuration Register 3 (CHGCONFIG3) (Address = 0x06) [reset = 0xB2]
        1. Table 8. CHGCONFIG3 Register Field Descriptions
      9. 8.6.9  WLED Control Register 1 (WLEDCTRL1) (Address = 0x07) [reset = 0xB1]
        1. Table 9. WLEDCTRL1 Register Field Descriptions
      10. 8.6.10 WLED Control Register 2 (WLEDCTRL2) (Address = 0x08) [reset = 0x00]
        1. Table 10. WLEDCTRL2 Register Field Descriptions
      11. 8.6.11 MUX Control Register (MUXCTRL) (Address = 0x09) [reset = 0x00]
        1. Table 11. MUXCTRL Register Field Descriptions
      12. 8.6.12 Status Register (STATUS) (Address = 0x0A) [reset = 0x00]
        1. Table 12. STATUS Register Field Descriptions
      13. 8.6.13 Password Register (PASSWORD) (Address = 0x0B) [reset = 0x00]
        1. Table 13. Password Register (PASSWORD) Field Descriptions
      14. 8.6.14 Power Good Register (PGOOD) (Address = 0x0C) [reset = 0x00]
        1. Table 14. PGOOD Register Field Descriptions
      15. 8.6.15 Power-Good Control Register (DEFPG) (Address = 0x0D) [reset = 0x0C]
        1. Table 15. DEFPG Register Field Descriptions
      16. 8.6.16 DCDC1 Control Register (DEFDCDC1) (Address = 0x0E) [reset = X]
        1. Table 16. DEFDCDC1 Register Field Descriptions
      17. 8.6.17 DCDC2 Control Register (DEFDCDC2) (Address = 0x0F) [reset = X]
        1. Table 17. DEFDCDC2 Register Field Descriptions
      18. 8.6.18 DCDC3 Control Register (DEFDCDC3) (Address = 0x10) [reset = 0x08]
        1. Table 18. DEFDCDC3 Register Field Descriptions
      19. 8.6.19 Slew-Rate Control Register (DEFSLEW) (Address = 0x11) [reset = 0x06]
        1. Table 19. DEFSLEW Register Field Descriptions
      20. 8.6.20 LDO1 Control Register (DEFLDO1) (Address = 0x12) [reset = 0x09]
        1. Table 20. DEFLDO1 Register Field Descriptions
      21. 8.6.21 LDO2 Control Register (DEFLDO2) (Address = 0x13) [reset = 0x38]
        1. Table 21. DEFLDO2 Register Field Descriptions
      22. 8.6.22 Load Switch1 or LDO3 Control Register (DEFLS1) (Address = 0x14) [reset = X]
        1. Table 22. DEFLS1 Register Field Descriptions
      23. 8.6.23 Load Switch2 or LDO4 Control Register (DEFLS2) (Address = 0x15) [reset = X]
        1. Table 23. DEFLS2 Register Field Descriptions
      24. 8.6.24 Enable Register (ENABLE) (Address = 0x16) [reset = 0x00]
        1. Table 24. ENABLE Register Field Descriptions
      25. 8.6.25 UVLO Control Register (DEFUVLO) (Address = 0x18) [reset = 0x03]
        1. Table 25. DEFUVLO Register Field Descriptions
      26. 8.6.26 Sequencer Register 1 (SEQ1) (Address = 0x19) [reset = X]
        1. Table 26. SEQ1 Register Field Descriptions
      27. 8.6.27 Sequencer Register 2 (SEQ2) (Address = 0x1A) [reset = X]
        1. Table 27. SEQ2 Register Field Descriptions
      28. 8.6.28 Sequencer Register 3 (SEQ3) (Address = 0x1B) [reset = X]
        1. Table 28. SEQ3 Register Field Descriptions
      29. 8.6.29 Sequencer Register 4 (SEQ4) (Address = 0x1C) [reset = 0x40]
        1. Table 29. SEQ4 Register Field Descriptions
      30. 8.6.30 Sequencer Register 5 (SEQ5) (Address = 0x1D) [reset = X]
        1. Table 30. SEQ5 Register Field Descriptions
      31. 8.6.31 Sequencer Register 6 (SEQ6) (Address = 0x1E) [reset = 0x00]
        1. Table 31. SEQ6 Register Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Filter Design (Inductor and Output Capacitor)
          1. 9.2.2.1.1 Inductor Selection for Buck Converters
          2. 9.2.2.1.2 Output Capacitor Selection
          3. 9.2.2.1.3 Input Capacitor Selection
        2. 9.2.2.2 5-V Operation Without a Battery
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

VBAT = 3.6 V ±5%, TJ = 27ºC (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT VOLTAGE AND CURRENTS
VBAT Battery input voltage range USB or AC supply connected 0 5.5 V
USB and AC not connected 2.75 5.5
VAC AC adapter input voltage range Valid range for charging 4.3 5.8 V
VUSB USB input voltage range Valid range for charging 4.3 5.8 V
VUVLO Undervoltage lockout Measured in respect to VBAT; supply falling;
VAC = VUSB = 0 V		 UVLO[1:0] = 00b 2.73 V
UVLO[1:0] = 01b 2.89
UVLO[1:0] = 10b 3.18
UVLO[1:0] = 11b 3.3
UVLO accuracy –2% 2%
UVLO deglitch time(3) 4 6 ms
VOFFSET AC and USB UVLO offset VBAT< VUVLO; Device shuts down when VAC, VUSB drop below VUVLO + VOFFSET 200 mV
IOFF OFF current,
Total current into VSYS, VINDCDCx, VINLDO		 All rails disabled, TA = 27°C 6 µA
ISLEEP Sleep current,
Total current into VSYS, VINDCDCx, VINLDO		 LDO1 and LDO2 enabled, no load.
All other rails disabled.
VSYS = 4 V, TA = 0.105°C		 80 106 µA
POWER PATH AC AND USB DETECTION LIMITS
VIN(DT) AC and USB voltage-detection threshold VBAT> VUVLO, AC and USB valid when VAC-USB – VBAT> VIN(DT) 190 mV
VBAT< VUVLO, AC and USB valid when VAC-USB> VIN(DT) 4.3 V
VIN(NDT) AC and USB voltage-removal detection threshold VBAT> VUVLO, AC and USB invalid when VAC/USB – VBAT< VIN(DT) 125 mV
VBAT< VUVLO, AC and USB invalid when VAC-USB< VIN(DT) VUVLO + VOFFSET V
tRISE VAC, VUSB rise time Voltage rising from 100 mV to 4.5 V. If rise time is exceeded, device may not power up. 50 ms
tDG(DT) Power detected deglitch(3) AC or USB voltage increasing 22.5 ms
VIN(OVP) Input overvoltage detection threshold USB and AC input 5.8 6 6.4 V
POWER PATH TIMING
tSW(PSEL) Switching from AC to USB(3) 150 µs
POWER PATH MOSFET CHARACTERISTICS
VDO, AC AC input switch dropout voltage IAC[1:0] = 11b (2.5 A), ISYS = 1 A 150 mV
VDO, USB USB input switch dropout voltage IUSB[1:0] = 01b (500 mA), ISYS = 500 mA 100 mV
IUSB[1:0] = 10b (1300 mA), ISYS = 800 mA 160
VDO, BAT Battery switch dropout voltage VBAT = 3 V, IBAT = 1 A 60 mV
POWER PATH INPUT CURRENT LIMITS
IACLMT Input current limit; AC pin IAC[1:0] = 00b 90 130 mA
IAC[1:0] = 01b 480 580
IAC[1:0] = 10b 1000 1500
IAC[1:0] = 11b 2000 2500
IUSBLMT Input current limit; USB pin IUSB[1:0] = 00b 90 100 mA
IUSB[1:0] = 01b 460 500
IUSB[1:0] = 10b 1000 1300
IUSB[1:0] = 11b 1500 1800
IBAT Battery load current(3) 2 A
POWER PATH BATTERY SUPPLEMENT DETECTION
VBSUP Battery supplement threshold VSYS ≤ VBAT – VBSUP1,
VSYS falling IUSB[1:0] = 10b 		40 mV
Battery supplement hysteresis VSYS rising 20
POWER PATH BATTERY PROTECTION
VBAT(SC) BAT pin short-circuit detection threshold 1.3 1.5 1.7 V
IBAT(SC) Source current for BAT pin short-circuit detection 7.5 mA
INPUT BASED DYNAMIC POWER PATH MANAGEMENT (DPPM)
VDPPM Threshold at which DPPM loop is enabled I2C selectable 3.5 4.25 V
BATTERY CHARGER
VOREG Battery charger voltage I2C selectable 4.1 4.25 V
Battery charger accuracy –2% 1%
VLOWV Precharge to fast-charge transition threshold VPRECHG = 0b 2.9 V
VPRECHG = 1b 2.5
tDGL1(LOWV) Deglitch time on precharge to fast-charge transition(3) 25 ms
tDGL2(LOWV) Deglitch time on fast-charge to precharge transition(3) 25 ms
ICHG Battery fast charge current range
VOREG> VBAT> VLOWV,
VIN = VUSB = 5 V 		ICHRG[1:0] = 00b 300 mA
ICHRG[1:0] = 01b 400
ICHRG[1:0] = 10b 450 500 550
ICHRG[1:0] = 11b 700
IPRECHG Precharge current ICHRG[1:0] = 00b 30 mA
ICHRG[1:0] = 01b 40
ICHRG[1:0] = 10b 25 50 75
ICHRG[1:0] = 11b 70
ITERM Charge current value for termination detection threshold (fraction of ICHG) TERMIF[1:0] = 00b 2.5%
TERMIF[1:0] = 01b 3% 7.5% 10%
TERMIF[1:0] = 10b 15%
TERMIF[1:0] = 11b 18%
tDGL(TERM) Deglitch time, termination detected(3) 125 ms
VRCH Recharge detection threshold Voltage below VOREG 150 100 70 mV
tDGL(RCH) Deglitch time, recharge threshold detected(3) 125 ms
IBAT(DET) Sink current for battery detection TJ = 27°C 3 7.5 10 mA
tDET Battery detection timer. IBAT(DET) is pulled from the battery for tDET. If BAT voltage stays above VRCH threshold the battery is connected.(3) VBAT< VRCH; 250 ms
tCHG Charge safety timer(3) Safety timer range, thermal and DPPM not active, selectable by I2C 4 8 h
tPRECHG Precharge timer(3) Pre charge timer, thermal and DPPM loops not active, selectable by I2C PCHRGT = 0b 30 60 min
PCHRGT = 1b 60
BATTERY NTC MONITOR
tTHON Thermistor power on time at charger off, sampling mode on 10 ms
tTHOFF Thermistor power sampling period at charger off, sampling mode on 1 s
RNTC_PULL Pullup resistor from thermistor to Internal LDO, I2C selectable NTC_TYPE = 1 (10-kΩ NTC) 7.35 kΩ
NTC_TYPE = 0 (100-kΩ NTC) 60.5
Accuracy TA = 27°C –3% 3%
VLTF Low-temperature failure threshold Temperature falling 1660 mV
Temperature rising 1610
VHTF High-temperature failure threshold Temperature falling TRANGE = 0b 910 mV
Temperature rising 860
Temperature falling TRANGE = 1b 667
Temperature rising 622
VDET Thermistor detection threshold 1750 1850 mV
tBATDET Thermistor not detected. Battery not present deglitch(3) 26 ms
THERMAL REGULATION
TJ(REG) Temperature regulation limit, temperature at which charge current is decreased 111 123 °C
DCDC1 (BUCK)
VIN Input voltage range VIN_DCDC1 pin 2.7 VSYS V
IQ,SLEEP Quiescent current in SLEEP mode No load, VSYS = 4 V, TA = 25°C 30 µA
VOUT Output voltage range External resistor divider (XADJ1 = 1b) 0.6 VIN V
I2C selectable in 25-mV steps
(XADJ1 = 0b)		 0.9 1.8(1)
DC output voltage accuracy VIN = VOUT + 0.3 V to 5.8 V;
0 mA ≤ IOUT ≤ 1.2 A		 –2% 3%
Power-save mode (PSM) ripple voltage IOUT = 1 mA, PFM mode
L = 2.2 µH, COUT = 20 µF		 40 mVpp
IOUT Output current range 0 1.2 A
rDS(on) High-side MOSFET on-resistance VIN = 2.7 V 170 mΩ
Low-side MOSFET on-resistance VIN = 2.7 V 120
ILEAK High-side MOSFET leakage current VIN = 5.8 V 2 µA
Low-side MOSFET leakage current VDS = 5.8 V 1
ILIMIT Current limit (high- and low-side MOSFET). 2.7 V < VIN< 5.8 V 1.6 A
fSW Switching frequency 1.95 2.25 2.55 MHz
VFB Feedback voltage XADJ = 1b 600 mV
tSS Soft-start time Time to ramp VOUT from 5% to 95%, no load 750 µs
RDIS Internal discharge resistor at L1(2) 250 Ω
L Inductor 1.5 2.2 µH
COUT Output capacitor Ceramic 10 22 µF
ESR of output capacitor 20 mΩ
DCDC2 (BUCK)
VIN Input voltage range VIN_DCDC2 pin 2.7 VSYS V
IQ,SLEEP Quiescent current in SLEEP mode No load, VSYS = 4 V, TA = 25°C 30 µA
VOUT Output voltage range External resistor divider (XADJ2 = 1b) 0.6 VIN V
I2C selectable in 25-mV steps
(XADJ2 = 0b)		 0.9 3.3
DC output voltage accuracy VIN = VOUT + 0.3 V to 5.8 V;
0 mA ≤ IOUT ≤ 1.2 A		 –2% 3%
Power-save mode (PSM) ripple voltage IOUT = 1 mA, PFM mode
L = 2.2 µH, COUT = 20 µF		 40 mVpp
IOUT Output current range 0 1.2 A
rDS(on) High-side MOSFET on-resistance VIN = 2.7 V 170 mΩ
Low-side MOSFET on-resistance VIN = 2.7 V 120
ILEAK High-side MOSFET leakage current VIN = 5.8 V 2 µA
Low-side MOSFET leakage current VDS = 5.8 V 1
ILIMIT Current limit (high and low side MOSFET). 2.7 V < VIN< 5.8 V 1.6 A
fSW Switching frequency 1.95 2.25 2.55 MHz
VFB Feedback voltage XADJ = 1b 600 mV
tSS Soft-start time Time to ramp VOUT from 5% to 95%, no load 750 µs
RDIS Internal discharge resistor at L2 250 Ω
L Inductor 1.5 2.2 µH
COUT Output capacitor Ceramic 10 22 µF
ESR of output capacitor 20 mΩ
DCDC3 (BUCK)
VIN Input voltage range VIN_DCDC3 pin 2.7 VSYS V
IQ,SLEEP Quiescent current in SLEEP mode No load, VSYS = 4 V, TA = 25°C 30 µA
VOUT Output voltage range External resistor divider (XADJ3 = 1b) 0.6 VIN V
I2C selectable in 25-mV steps
(XADJ3 = 0b)		 0.9 1.5(1)
DC output voltage accuracy VIN = VOUT + 0.3 V to 5.8 V;
0 mA ≤ IOUT ≤ 1.2 A		 –2% 3%
Power save mode (PSM) ripple voltage IOUT = 1 mA, PFM mode
L = 2.2 µH, COUT = 20 µF		 40 mVpp
IOUT Output current range 0 1.2 A
rDS(on) High-side MOSFET on-resistance VIN = 2.7 V 170 mΩ
Low side MOSFET on-resistance VIN = 2.7 V 120
ILEAK High-side MOSFET leakage current VIN = 5.8 V 2 µA
Low-side MOSFET leakage current VDS = 5.8 V 1
ILIMIT Current limit (high- and low-side MOSFET). 2.7 V < VIN< 5.8 V 1.6 A
fSW Switching frequency 1.95 2.25 2.55 MHz
VFB Feedback voltage XADJ = 1b 600 mV
tSS Soft-start time Time to ramp VOUT from 5% to 95%, no load 750 µs
RDIS Internal discharge resistor at L1, L2 250 Ω
L Inductor 1.5 2.2 µH
COUT Output capacitor Ceramic 10 22 µF
ESR of output capacitor 20 mΩ
LDO1, LDO2
VIN Input voltage range 1.8 5.8 V
IQ,SLEEP Quiescent current in SLEEP mode No load, VSYS = 4 V, TA = 25°C 5 µA
VOUT Output voltage range LDO1, I2C selectable 1 3.3 V
LDO2, I2C selectable 0.9 3.3
DC output voltage accuracy IOUT = 10 mA, VIN> VOUT + 200 mV,
VOUT> 0.9 V		 –2% 2%
Line regulation VIN = 2.7 V - 5.5 V, VOUT = 1.2 V,
IOUT = 100 mA		 –1% 1%
Load regulation IOUT = 1 mA - 100 mA, VOUT = 1.2 V,
VIN = 3.3 V		 –1% 1%
IOUT = 0 mA - 1 mA, VOUT = 1.2 V,
VIN = 3.3 V		 –2.5% 2.5%
IOUT Output current range SLEEP state 0 1 mA
ACTIVE state 0 100
ISC Short circuit current limit Output shorted to GND 100 250 mA
VDO Dropout voltage IOUT = 100 mA, VIN = 3.3 V 200 mV
RDIS Internal discharge resistor at output 430 Ω
COUT Output capacitor Ceramic 2.2 µF
ESR of output capacitor 20 mΩ
LS1 OR LDO3, AND LS2 OR LDO4, CONFIGURED AS LDOs
VIN Input voltage range 2.7 5.8 V
IQ,SLEEP Quiescent current in SLEEP mode No load, VSYS = 4 V, TA = 25°C 30 µA
VOUT Output voltage range LS1LDO3 = 1b, LS2LDO4 = 1b
I2C selectable 		1.5 3.3 V
DC output voltage accuracy IOUT = 10 mA, VIN> VOUT + 200 mV,
VOUT> 1.8 V		 –2% 2%
Line regulation VIN = 2.7 V - 5.5 V, VOUT = 1.8 V,
IOUT = 200 mA		 –1% 1%
Load regulation IOUT = 1 mA - 200 mA, VOUT = 1.8 V,
VIN = 3.3 V		 –1% 1%
IOUT Output current range TPS65217A 0 200 mA
TPS65217B 0 200
TPS65217C 0 400
TPS65217D 0 400
ISC Short-circuit current limit Output shorted to GND TPS65217A 200 280 mA
TPS65217B 200 280
TPS65217C 400 480
TPS65217D 400 480
VDO Dropout voltage IOUT = 200 mA, VIN = 3.3 V 200 mV
RDIS Internal discharge resistor at output(2) 375 Ω
COUT Output capacitor Ceramic 8 10 12 µF
ESR of output capacitor 20 mΩ
LS1 OR LDO3, AND LS2 OR LDO4, CONFIGURED AS LOAD SWITCHES
VIN Input voltage range LS1_VIN, LS2_VIN pins 1.8 5.8 V
RDS(ON) P-channel MOSFET on-resistance VIN = 1.8 V, over full temperature range 300 650 mΩ
ISC Short circuit current limit Output shorted to GND 200 280 mA
RDIS Internal discharge resistor at output 375 Ω
COUT Output capacitor Ceramic 1 10 12 µF
ESR of output capacitor 20 mΩ
WLED BOOST
VIN Input voltage range 2.7 5.8 V
VOUT Max output voltage ISINK = 20 mA 32 V
VOVP Output overvoltage protection 37 38 39 V
RDS(ON) N-channel MOSFET on-resistance VIN = 3.6 V 0.6 Ω
ILEAK N-channel leakage current VDS = 25 V, TA = 25°C 2 µA
ILIMIT N-channel MOSFET current limit 1.6 1.9 A
fSW Switching frequency 1.125 MHz
IINRUSH Inrush current on start-up VIN = 3.6 V, 1% duty cycle setting 1.1 A
VIN = 3.6 V, 100% duty cycle setting 2.1
L Inductor 18 µH
COUT Output capacitor Ceramic 4.7 µF
ESR of output capacitor 20 mΩ
WLED CURRENT SINK1, SINK2
VSINK1,2 Overvoltage protection threshold at ISINK1, ISINK2 pins 19 V
VDO, SINK1,2 Current sink drop-out voltage Measured from ISINK to GND 400 mV
VISET1,2 ISET1, ISET2 pin voltage 1.24 V
ISINK1,2 WLED current range (ISINK1, ISINK2) 1 25 mA
WLED sink current RISET = 130.0 kΩ 10
RISET = 86.6 kΩ 15
RISET = 64.9 kΩ 20
RISET = 52.3 kΩ 25
DC current set accuracy ISINK = 5 mA to 25 mA, 100% duty cycle –5% 5%
DC current matching RSET1 = 52.3 kΩ, ISINK = 25 mA,
VBAT = 3.6 V, 100% duty cycle		 –5% 5%
RSET1 = 130 kΩ, ISINK = 10 mA,
VBAT = 3.6 V, 100% duty cycle		 –5% 5%
fPWM PWM dimming frequency FDIM[1:0] = 00b 100 Hz
FDIM[1:0] = 01b 200
FDIM[1:0] = 10b 500
FDIM[1:0] = 11b 1000
ANALOG MULTIPLEXER
g Gain, VBAT (VBAT / VOUT,MUX); VSYS (VSYS / VOUT,MUX) 3 V/V
Gain, VTS (VTS / VOUT,MUX); MUX_IN (VMUX_IN / VMUX_OUT) 1
Gain, VICHARGE (VOUT,MUX / VICHARGE) ICHRG[1:0] = 00b 7.575 V/A
ICHRG[1:0] = 01b 5.625
ICHRG[1:0] = 10b 4.5
ICHRG[1:0] = 11b 3.214
VOUT Buffer headroom (VSYS – VMUX_OUT) VSYS = 3.6 V, MUX[2:0] = 101b
(VMUX_IN – VMUX_OUT) / VMUX_IN> 1% 		0.7 1 V
ROUT Output Impedance 180 Ω
ILEAK Leakage current MUX[2:0] = 000b (HiZ), VMUX = 2.25 V 1 µA
LOGIC LEVELS AND TIMING CHARACTERISTICS
(SCL, SDA, PB_IN, PGOOD, LDO_PGOOD, PWR_EN, nINT, nWAKEUP, nRESET)
PGTH PGOOD comparator treshold,
All DC/DC converters and LDOs(3) 		Output voltage falling, % of set voltage 90%
Output voltage rising, % of set voltage 95%
PGDG PGOOD deglitch time Output voltage falling, DCDC1, DCDC2, DCDC3 2 4 ms
Output voltage falling, LDO1, LDO2, LDO3, LDO4 1 2
PGDLY PGOOD delay time PGDLY[1:0] = 00b 20 ms
PGDLY[1:0] = 01b 100
PGDLY[1:0] = 10b 200
PGDLY[1:0] = 11b 400
tHRST PB-IN hard-reset-detect time(3) 8 s
tDG PB_IN pin deglitch time(3) 50 ms
PWR_EN pin deglitch time(3) 50
nRESET pin deglitch time(3) 30
RPULLUP PB_IN internal pullup resistor 100 kΩ
nRESET internal pullup resistor 100
VIH High-level input voltage
PB_IN, SCL, SDA, PWR_EN, nRESET 		1.2 VIN V
VIL Low-level input voltage
PB_IN, SCL, SDA, PWR_EN, nRESET 		0 0.4 V
IBIAS Input bias current
PB_IN, SCL, SDA 		0.01 1 µA
VOL Output low voltage nINT, nWAKEUP, IO = 1 mA 0.3 V
PGOOD, LDO_PGOOD, IO = 1 mA 0.3
VOH Output high voltage PGOOD, LDO_PGOOD, IO = 1 mA VIO – 0.3 V
ILEAK Pin leakage current
nINT, nWAKEUP 		Pin pulled up to 3.3-V supply 0.2 µA
I2C slave address 0x24h
OSCILLATOR
fOSC Oscillator frequency 9 MHz
Oscillator frequency accuracy TA = –40°C to 105°C –10% 10%
OVERTEMPERATURE SHUTDOWN
TOTS Overtemperature shutdown Increasing junction temperature 150 °C
Hysteresis Decreasing junction temperature 20 °C
(1) Contact factory for 3.3-V option.
(2) Can be factory disabled.
(3) Not tested in production