SLVSB64I
November 2011 – March 2018
TPS65217
PRODUCTION DATA.
1
Features
2
Applications
3
Description
Device Images
Simplified Application Diagram
4
Revision History
5
Device Comparison Table
6
Pin Configuration and Functions
Pin Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
I2C Timing Requirements
7.7
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Wake-Up and Power-Up Sequencing
8.3.1.1
Power-Up Sequencing
8.3.1.2
Power-Down Sequencing
8.3.1.3
Special Strobes (STROBE 14 and 15)
8.3.2
Power Good
8.3.2.1
LDO1, LDO2 Power-Good (LDO_PGOOD)
8.3.2.2
Primary Power-Good (PGOOD)
8.3.2.3
Load Switch PGOOD
8.3.3
Push-Button Monitor (PB_IN)
8.3.4
nWAKEUP Pin (nWAKEUP)
8.3.5
Power Enable Pin (PWR_EN)
8.3.6
Reset Pin (nRESET)
8.3.7
Interrupt Pin (nINT)
8.3.8
Analog Multiplexer
8.3.9
Battery Charger and Power Path
8.3.9.1
Shorted or Absent Battery (VBAT < 1.5 V)
8.3.9.2
Dead Battery (1.5 V < VBAT < VUVLO)
8.3.9.3
Good Battery (VBAT > VUVLO)
8.3.9.4
AC and USB Input Discharge
8.3.10
Battery Charging
8.3.11
Precharge
8.3.12
Charge Termination
8.3.13
Battery Detection and Recharge
8.3.14
Safety Timer
8.3.14.1
Dynamic Timer Function
8.3.14.2
Timer Fault
8.3.15
Battery-Pack Temperature Monitoring
8.3.16
DC/DC Converters
8.3.16.1
Operation
8.3.16.2
Output Voltage Setting
8.3.16.3
Power-Save Mode and Pulse-Frequency Modulation (PFM)
8.3.16.4
Dynamic Voltage Positioning
8.3.16.5
100% Duty-Cycle Low-Dropout Operation
8.3.16.6
Short-Circuit Protection
8.3.16.7
Soft Start
8.3.17
Standby LDO Regulators (LDO1, LDO2)
8.3.18
Load Switches or LDO Regulators (LS1 or LDO3, LS2 or LDO4)
8.3.19
White LED Driver
8.4
Device Functional Modes
8.4.1
PMIC States
8.4.1.1
OFF State
8.4.1.2
ACTIVE State
8.4.1.3
SLEEP State
8.4.1.4
RESET State
8.5
Programming
8.5.1
I2C Bus Operation
8.5.2
Password Protection
8.5.2.1
Level1 Protection
8.5.2.2
Level2 Protection
8.5.3
Resetting of Registers to Default Values
8.6
Register Maps
8.6.1
Register Address Map
8.6.2
Chip ID Register (CHIPID) (Address = 0x00) [reset = X]
Table 2.
CHIPID Register Field Descriptions
8.6.3
Power Path Control Register (PPATH) (Address = 0x01) [reset = 0x3D]
Table 3.
PPATH Register Field Descriptions
8.6.4
Interrupt Register (INT) (Address = 0x02) [reset = 0x80]
Table 4.
INT Register Field Descriptions
8.6.5
Charger Configuration Register 0 (CHGCONFIG0) (Address = 0x03) [reset = 0x00]
Table 5.
CHGCONFIG0 Register Field Descriptions
8.6.6
Charger Configuration Register 1 (CHGCONFIG1) (Address = 0x04) [reset = 0xB1]
Table 6.
CHGCONFIG1 Register Field Descriptions
8.6.7
Charger Configuration Register 2 (CHGCONFIG2) (Address = 0x05) [reset = 0x80]
Table 7.
CHGCONFIG2 Register Field Descriptions
8.6.8
Charger Configuration Register 3 (CHGCONFIG3) (Address = 0x06) [reset = 0xB2]
Table 8.
CHGCONFIG3 Register Field Descriptions
8.6.9
WLED Control Register 1 (WLEDCTRL1) (Address = 0x07) [reset = 0xB1]
Table 9.
WLEDCTRL1 Register Field Descriptions
8.6.10
WLED Control Register 2 (WLEDCTRL2) (Address = 0x08) [reset = 0x00]
Table 10.
WLEDCTRL2 Register Field Descriptions
8.6.11
MUX Control Register (MUXCTRL) (Address = 0x09) [reset = 0x00]
Table 11.
MUXCTRL Register Field Descriptions
8.6.12
Status Register (STATUS) (Address = 0x0A) [reset = 0x00]
Table 12.
STATUS Register Field Descriptions
8.6.13
Password Register (PASSWORD) (Address = 0x0B) [reset = 0x00]
Table 13.
Password Register (PASSWORD) Field Descriptions
8.6.14
Power Good Register (PGOOD) (Address = 0x0C) [reset = 0x00]
Table 14.
PGOOD Register Field Descriptions
8.6.15
Power-Good Control Register (DEFPG) (Address = 0x0D) [reset = 0x0C]
Table 15.
DEFPG Register Field Descriptions
8.6.16
DCDC1 Control Register (DEFDCDC1) (Address = 0x0E) [reset = X]
Table 16.
DEFDCDC1 Register Field Descriptions
8.6.17
DCDC2 Control Register (DEFDCDC2) (Address = 0x0F) [reset = X]
Table 17.
DEFDCDC2 Register Field Descriptions
8.6.18
DCDC3 Control Register (DEFDCDC3) (Address = 0x10) [reset = 0x08]
Table 18.
DEFDCDC3 Register Field Descriptions
8.6.19
Slew-Rate Control Register (DEFSLEW) (Address = 0x11) [reset = 0x06]
Table 19.
DEFSLEW Register Field Descriptions
8.6.20
LDO1 Control Register (DEFLDO1) (Address = 0x12) [reset = 0x09]
Table 20.
DEFLDO1 Register Field Descriptions
8.6.21
LDO2 Control Register (DEFLDO2) (Address = 0x13) [reset = 0x38]
Table 21.
DEFLDO2 Register Field Descriptions
8.6.22
Load Switch1 or LDO3 Control Register (DEFLS1) (Address = 0x14) [reset = X]
Table 22.
DEFLS1 Register Field Descriptions
8.6.23
Load Switch2 or LDO4 Control Register (DEFLS2) (Address = 0x15) [reset = X]
Table 23.
DEFLS2 Register Field Descriptions
8.6.24
Enable Register (ENABLE) (Address = 0x16) [reset = 0x00]
Table 24.
ENABLE Register Field Descriptions
8.6.25
UVLO Control Register (DEFUVLO) (Address = 0x18) [reset = 0x03]
Table 25.
DEFUVLO Register Field Descriptions
8.6.26
Sequencer Register 1 (SEQ1) (Address = 0x19) [reset = X]
Table 26.
SEQ1 Register Field Descriptions
8.6.27
Sequencer Register 2 (SEQ2) (Address = 0x1A) [reset = X]
Table 27.
SEQ2 Register Field Descriptions
8.6.28
Sequencer Register 3 (SEQ3) (Address = 0x1B) [reset = X]
Table 28.
SEQ3 Register Field Descriptions
8.6.29
Sequencer Register 4 (SEQ4) (Address = 0x1C) [reset = 0x40]
Table 29.
SEQ4 Register Field Descriptions
8.6.30
Sequencer Register 5 (SEQ5) (Address = 0x1D) [reset = X]
Table 30.
SEQ5 Register Field Descriptions
8.6.31
Sequencer Register 6 (SEQ6) (Address = 0x1E) [reset = 0x00]
Table 31.
SEQ6 Register Field Descriptions
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Output Filter Design (Inductor and Output Capacitor)
9.2.2.1.1
Inductor Selection for Buck Converters
9.2.2.1.2
Output Capacitor Selection
9.2.2.1.3
Input Capacitor Selection
9.2.2.2
5-V Operation Without a Battery
9.2.3
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Device Support
12.1.1
Third-Party Products Disclaimer
12.2
Documentation Support
12.2.1
Related Documentation
12.3
Receiving Notification of Documentation Updates
12.4
Community Resources
12.5
Trademarks
12.6
Electrostatic Discharge Caution
12.7
Glossary
13
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RSL|48
MPQF193A
Thermal pad, mechanical data (Package|Pins)
RSL|48
QFND160K
Orderable Information
slvsb64i_oa
slvsb64i_pm
7.2
ESD Ratings
VALUE
UNIT
V
(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
±2000
V
Charged-device model (CDM), per JEDEC specification JESD22-C101
(2)
±500
(1)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2)
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.