SLVSB64I November   2011  – March 2018 TPS65217

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Application Diagram
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Wake-Up and Power-Up Sequencing
        1. 8.3.1.1 Power-Up Sequencing
        2. 8.3.1.2 Power-Down Sequencing
        3. 8.3.1.3 Special Strobes (STROBE 14 and 15)
      2. 8.3.2  Power Good
        1. 8.3.2.1 LDO1, LDO2 Power-Good (LDO_PGOOD)
        2. 8.3.2.2 Primary Power-Good (PGOOD)
        3. 8.3.2.3 Load Switch PGOOD
      3. 8.3.3  Push-Button Monitor (PB_IN)
      4. 8.3.4  nWAKEUP Pin (nWAKEUP)
      5. 8.3.5  Power Enable Pin (PWR_EN)
      6. 8.3.6  Reset Pin (nRESET)
      7. 8.3.7  Interrupt Pin (nINT)
      8. 8.3.8  Analog Multiplexer
      9. 8.3.9  Battery Charger and Power Path
        1. 8.3.9.1 Shorted or Absent Battery (VBAT < 1.5 V)
        2. 8.3.9.2 Dead Battery (1.5 V < VBAT < VUVLO)
        3. 8.3.9.3 Good Battery (VBAT > VUVLO)
        4. 8.3.9.4 AC and USB Input Discharge
      10. 8.3.10 Battery Charging
      11. 8.3.11 Precharge
      12. 8.3.12 Charge Termination
      13. 8.3.13 Battery Detection and Recharge
      14. 8.3.14 Safety Timer
        1. 8.3.14.1 Dynamic Timer Function
        2. 8.3.14.2 Timer Fault
      15. 8.3.15 Battery-Pack Temperature Monitoring
      16. 8.3.16 DC/DC Converters
        1. 8.3.16.1 Operation
        2. 8.3.16.2 Output Voltage Setting
        3. 8.3.16.3 Power-Save Mode and Pulse-Frequency Modulation (PFM)
        4. 8.3.16.4 Dynamic Voltage Positioning
        5. 8.3.16.5 100% Duty-Cycle Low-Dropout Operation
        6. 8.3.16.6 Short-Circuit Protection
        7. 8.3.16.7 Soft Start
      17. 8.3.17 Standby LDO Regulators (LDO1, LDO2)
      18. 8.3.18 Load Switches or LDO Regulators (LS1 or LDO3, LS2 or LDO4)
      19. 8.3.19 White LED Driver
    4. 8.4 Device Functional Modes
      1. 8.4.1 PMIC States
        1. 8.4.1.1 OFF State
        2. 8.4.1.2 ACTIVE State
        3. 8.4.1.3 SLEEP State
        4. 8.4.1.4 RESET State
    5. 8.5 Programming
      1. 8.5.1 I2C Bus Operation
      2. 8.5.2 Password Protection
        1. 8.5.2.1 Level1 Protection
        2. 8.5.2.2 Level2 Protection
      3. 8.5.3 Resetting of Registers to Default Values
    6. 8.6 Register Maps
      1. 8.6.1  Register Address Map
      2. 8.6.2  Chip ID Register (CHIPID) (Address = 0x00) [reset = X]
        1. Table 2. CHIPID Register Field Descriptions
      3. 8.6.3  Power Path Control Register (PPATH) (Address = 0x01) [reset = 0x3D]
        1. Table 3. PPATH Register Field Descriptions
      4. 8.6.4  Interrupt Register (INT) (Address = 0x02) [reset = 0x80]
        1. Table 4. INT Register Field Descriptions
      5. 8.6.5  Charger Configuration Register 0 (CHGCONFIG0) (Address = 0x03) [reset = 0x00]
        1. Table 5. CHGCONFIG0 Register Field Descriptions
      6. 8.6.6  Charger Configuration Register 1 (CHGCONFIG1) (Address = 0x04) [reset = 0xB1]
        1. Table 6. CHGCONFIG1 Register Field Descriptions
      7. 8.6.7  Charger Configuration Register 2 (CHGCONFIG2) (Address = 0x05) [reset = 0x80]
        1. Table 7. CHGCONFIG2 Register Field Descriptions
      8. 8.6.8  Charger Configuration Register 3 (CHGCONFIG3) (Address = 0x06) [reset = 0xB2]
        1. Table 8. CHGCONFIG3 Register Field Descriptions
      9. 8.6.9  WLED Control Register 1 (WLEDCTRL1) (Address = 0x07) [reset = 0xB1]
        1. Table 9. WLEDCTRL1 Register Field Descriptions
      10. 8.6.10 WLED Control Register 2 (WLEDCTRL2) (Address = 0x08) [reset = 0x00]
        1. Table 10. WLEDCTRL2 Register Field Descriptions
      11. 8.6.11 MUX Control Register (MUXCTRL) (Address = 0x09) [reset = 0x00]
        1. Table 11. MUXCTRL Register Field Descriptions
      12. 8.6.12 Status Register (STATUS) (Address = 0x0A) [reset = 0x00]
        1. Table 12. STATUS Register Field Descriptions
      13. 8.6.13 Password Register (PASSWORD) (Address = 0x0B) [reset = 0x00]
        1. Table 13. Password Register (PASSWORD) Field Descriptions
      14. 8.6.14 Power Good Register (PGOOD) (Address = 0x0C) [reset = 0x00]
        1. Table 14. PGOOD Register Field Descriptions
      15. 8.6.15 Power-Good Control Register (DEFPG) (Address = 0x0D) [reset = 0x0C]
        1. Table 15. DEFPG Register Field Descriptions
      16. 8.6.16 DCDC1 Control Register (DEFDCDC1) (Address = 0x0E) [reset = X]
        1. Table 16. DEFDCDC1 Register Field Descriptions
      17. 8.6.17 DCDC2 Control Register (DEFDCDC2) (Address = 0x0F) [reset = X]
        1. Table 17. DEFDCDC2 Register Field Descriptions
      18. 8.6.18 DCDC3 Control Register (DEFDCDC3) (Address = 0x10) [reset = 0x08]
        1. Table 18. DEFDCDC3 Register Field Descriptions
      19. 8.6.19 Slew-Rate Control Register (DEFSLEW) (Address = 0x11) [reset = 0x06]
        1. Table 19. DEFSLEW Register Field Descriptions
      20. 8.6.20 LDO1 Control Register (DEFLDO1) (Address = 0x12) [reset = 0x09]
        1. Table 20. DEFLDO1 Register Field Descriptions
      21. 8.6.21 LDO2 Control Register (DEFLDO2) (Address = 0x13) [reset = 0x38]
        1. Table 21. DEFLDO2 Register Field Descriptions
      22. 8.6.22 Load Switch1 or LDO3 Control Register (DEFLS1) (Address = 0x14) [reset = X]
        1. Table 22. DEFLS1 Register Field Descriptions
      23. 8.6.23 Load Switch2 or LDO4 Control Register (DEFLS2) (Address = 0x15) [reset = X]
        1. Table 23. DEFLS2 Register Field Descriptions
      24. 8.6.24 Enable Register (ENABLE) (Address = 0x16) [reset = 0x00]
        1. Table 24. ENABLE Register Field Descriptions
      25. 8.6.25 UVLO Control Register (DEFUVLO) (Address = 0x18) [reset = 0x03]
        1. Table 25. DEFUVLO Register Field Descriptions
      26. 8.6.26 Sequencer Register 1 (SEQ1) (Address = 0x19) [reset = X]
        1. Table 26. SEQ1 Register Field Descriptions
      27. 8.6.27 Sequencer Register 2 (SEQ2) (Address = 0x1A) [reset = X]
        1. Table 27. SEQ2 Register Field Descriptions
      28. 8.6.28 Sequencer Register 3 (SEQ3) (Address = 0x1B) [reset = X]
        1. Table 28. SEQ3 Register Field Descriptions
      29. 8.6.29 Sequencer Register 4 (SEQ4) (Address = 0x1C) [reset = 0x40]
        1. Table 29. SEQ4 Register Field Descriptions
      30. 8.6.30 Sequencer Register 5 (SEQ5) (Address = 0x1D) [reset = X]
        1. Table 30. SEQ5 Register Field Descriptions
      31. 8.6.31 Sequencer Register 6 (SEQ6) (Address = 0x1E) [reset = 0x00]
        1. Table 31. SEQ6 Register Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Filter Design (Inductor and Output Capacitor)
          1. 9.2.2.1.1 Inductor Selection for Buck Converters
          2. 9.2.2.1.2 Output Capacitor Selection
          3. 9.2.2.1.3 Input Capacitor Selection
        2. 9.2.2.2 5-V Operation Without a Battery
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

RSL Package
48-Pin VQFN With Exposed Thermal Pad
Top View
NC – No internal connection

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
AC 10 I AC-adapter input to power path. Connect this pin to an external dc supply.
AGND 41 — Analog ground (GND). Connect the AGND pin to the ground plane.
BAT 4, 5 I/O Battery charger output. Connect these pins to the battery.
BAT_SENSE 6 I Battery-voltage sense input. Connect the BAT_SENSE pin to the BAT pin directly at the battery terminal.
BYPASS 47 O Internal bias voltage (2.25 V). TI does not recommend connecting any external load to this pin.
FB_WLED 38 I Feedback pin for the WLED boost converter. This pin is also connected to the anode of the WLED strings.
INT_LDO 48 O Internal bias voltage (2.3 V). TI does not recommend connecting any external load to this pin.
ISET1 35 I Low-level WLED current set. Connect this pin to a resistor to ground to set the WLED low-level current value.
ISET2 36 I High-level WLED current set. Connect this pin to a resistor to ground to set the WLED high-level current value.
ISINK1 34 I Input to the WLED current SINK1. Connect this pin to the cathode of the WLED string. Current through the SINK1 pin equals current through the ISINK2 pin. If only one WLED string is used, short the ISINK1 and ISINK2 pins together.
ISINK2 33 I Input to the WLED current SINK2. Connect this pin to the cathode of the WLED string. Current through the SINK1 pin equals current through the ISINK2 pin. If only one WLED string is used, short the ISINK1 and ISINK2 pins together.
L1 20 O Switch pin for DCDC1. Connect this pin to the respective inductor.
L2 23 O Switch pin for DCDC2. Connect this pin to the respective inductor.
L3 31 O Switch pin for DCDC3. Connect this pin to the respective inductor.
L4 37 O Switch pin of the WLED boost converter. Connected this pin to the respective inductor.
LDO_PGOOD 46 O Power-good signal for the LDO regulator (LDO1 and LDO2 only). This pin is a push-pull output. This pin is pulled low when either the LDO1 or LDO2 regulator is out of regulation.
LS1_IN 39 I Input voltage pin for load switch 1 (LS1) or LDO3
LS1_OUT 40 O Output voltage pin for load switch 1 (LS1) or LDO3
LS2_IN 42 I Input voltage pin for load switch 2 (LS2) or LDO4
LS2_OUT 43 O Output voltage pin for load switch 2 (LS2) or LDO4
MUX_IN 14 O Input to analog multiplexer
MUX_OUT 16 O Output pin of analog multiplexer
NC 15, 17 Not used
nINT 45 O Interrupt output. This pin is an active-low, open-drain output. This pin is pulled low if an interrupt bit is set. The output goes high after the bit causing the interrupt in the INT register is read. The interrupt sources can be masked in the INT register, such that no interrupt is generated when the corresponding interrupt bit is set.
nRESET 44 I Reset pin. This pin is an active-low input. Pulling this pin low causes the PMIC to shut down. When this pin returns to a high voltage level, the PMIC powers up in its default state after a 1-s delay.
nWAKEUP 13 O Signal to the host to indicate a power-on event. This pin is an active-low, open-drain output.
PB_IN 25 I Push-button monitor input. This pin is typically connected to a momentary switch to ground. This pin is an active-low input.
PGND 30 Power ground. Connect this pin to the ground plane.
PGOOD 26 O Power-good output. This pin is a push-pull output. This pin is pulled low when any of the power rails are out of regulation.
PWR_EN 9 I Enable input for the DCDC1, DCDC2, and DCDC3 converters, and the LDO1, LDO2, LDO3, and LDO4 regulators. Pull this pin high to start the power-up sequence.
SCL 28 I Clock input for the I2C interface
SDA 27 I/O Data line for the I2C interface
SYS 7, 8 O System voltage pin and output of the power path. All voltage regulators are typically powered from this output.
TS 11 I Temperature sense input. Connect this pin to the NTC thermistor to sense the battery temperature. This pin works with 10-kΩ and 100-kΩ thermistors. For more information, see the Battery-Pack Temperature Monitoring section.
USB 12 I USB voltage input to power path. Connect this pin to an external voltage from a USB port.
VDCDC1 19 I DCDC1 output and feedback voltage-sense input
VDCDC2 24 I DCDC2 output and feedback voltage-sense input
VDCDC3 29 I DCDC3 output and feedback voltage-sense input
VINLDO 2 I Input voltage for LDO1 and LDO2
VIN_DCDC1 21 I Input voltage for DCDC1. This pin must be connected to the SYS pin.
VIN_DCDC2 22 I Input voltage for DCDC2. This pin must be connected to the SYS pin.
VIN_DCDC3 32 I Input voltage for DCDC3. This pin must be connected to the SYS pin.
VIO 18 I Output-high supply for output buffers
VLDO1 3 O Output voltage of LDO1
VLDO2 1 O Output voltage of LDO2
Thermal pad — Power-ground connection for the PMIC. Connect the thermal pad to the ground plane.