SLVSF11 June 2019 TPS652170
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
SEQ6 is shown in Figure 59 and described in Table 31.
Return to Summary Table.
This register is password protected.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DLY5[1:0] | DLY6[1:0] | Reserved | SEQUP | SEQDWN | INSTDWN | ||
R/W-00b | R/W-00b | R-0b | R/W-0b | R/W-0b | R/W-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7–6 | DLY5[1:0] | R/W, E2(1) | 00b |
Delay5 time 00b = 1 ms 01b = 2 ms 10b = 5 ms 11b = 10 ms |
5–4 | DLY6[1:0] | R/W, E2(1) | 00b |
Delay6 time 00b = 1 ms 01b = 2 ms 10b = 5 ms 11b = 10 ms |
3 | Reserved | R | 0b | This bit is reserved |
2 | SEQUP | R/W | 0b | Set this bit to 1b to trigger a power-up sequence. This bit is automatically reset to 0b. |
1 | SEQDWN | R/W | 0b | Set this bit to 1b to trigger a power-down sequence. This bit is automatically reset to 0b. |
0 | INSTDWN | R/W | 0b |
Instant shutdown bit
0b = Shutdown follows reverse power-up sequence 1b = All delays are bypassed and all rails are shut down at the same time. |