SLDS261 Data sheet

SLDS261A November 2019 – February 2021 TPS6521815

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

RSL|48
- MPQF193A

Thermal pad, mechanical data (Package|Pins)

RSL|48
- QFND155N

Orderable Information

7.5 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted).

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
INPUT VOLTAGE AND CURRENTS
V_{IN_BIAS}	Input supply voltage range	Normal operation		2.7		5.5	V
V_{IN_BIAS}	Input supply voltage range	EEPROM programming		4.5		5.5	V
	Deglitch time				5		ms
I_OFF	OFF state current, total current into IN_BIAS, IN_DCDCx, IN_LDO1, IN_LS	V_IN = 3.6 V; All rails disabled. T_J = 0°C to 85°C			5		µA
I_SUSPEND	SUSPEND current, total current into IN_BIAS, IN_DCDCx, IN_LDO1, IN_LS	V_IN = 3.6 V; DCDC3 enabled, low-power mode, no load. All other rails disabled. T_J = 0°C to 105°C			220		µA
SYS_BU
V_{SYS_BU}	SYS_BU voltage range	Powered from V_{IN_BU} or V_CC		2.2		5.5	V
C_{SYS_BU}	Recommended SYS_BU capacitor	Ceramic, X5R or X7R, see Table 9-3.			1		µF
C_{SYS_BU}	Tolerance	Ceramic, X5R or X7R, rated voltage ≥ 6.3 V		–20%		20%
INT_LDO
V_{INT_LDO}	Output voltage				2.5		V
V_{INT_LDO}	DC accuracy	I_OUT < 10 mA		–2%		2%
I_OUT	Output current range	Maximum allowable external load		0		10	mA
I_LIMIT	Short circuit current limit	Output shorted to GND			23		mA
t_HOLD	Hold-up time	Measured from V_{INT_LDO} = to V_{INT_LDO} = 1.8 V All rails enabled before power off, IN_BIAS tied to IN_DCDC1-4, IN_LDO1 V_{IN_BIAS} = 2.8 V to 0 V in < 5 µs No external load on INT_LDO C_{INT_LDO} = 1 µF, see Table 9-3.		150			ms
C_OUT	Nominal output capacitor value	Ceramic, X5R or X7R, see Table 9-3.		0.1	1	22	µF
C_OUT	Tolerance	Ceramic, X5R or X7R, rated voltage ≥ 6.3 V		–20%		20%
DCDC1 (1.1-V BUCK)
V_{IN_DCDC1}	Input voltage range	V_{IN_BIAS} > V_UVLO				5.5	V
V_DCDC1	Output voltage range	Adjustable through I²C		0.85		1.675	V
V_DCDC1	DC accuracy	2.7 V ≤ V_IN ≤ 5.5 V; 0 A ≤ I_OUT ≤ 1.8 A		–2%		2%
I_OUT	Continuous output current	V_{IN_DCDC1} > 2.7 V				1.8	A
I_Q	Quiescent current	Total current from I_{N_DCDC1} pin; Device not switching, no load			25	50	µA
R_DS(ON)	High-side FET on resistance	V_{IN_DCDC1} = 3.6 V			230	355	mΩ
R_DS(ON)	Low-side FET on resistance	V_{IN_DCDC1} = 3.6 V			90	145	mΩ
I_LIMIT	High-side current limit	V_{IN_DCDC1} = 3.6 V			2.8		A
I_LIMIT	Low-side current limit	V_{IN_DCDC1} = 3.6 V			3.1		A
V_PG	Power-good threshold	V_OUT falling	STRICT = 0b	88.5%	90%	91.5%
	Power-good threshold	V_OUT falling	STRICT = 1b	96%	96.5%	97%
	Hysteresis	V_OUT rising	STRICT = 0b	3.8%	4.1%	4.4%
	Hysteresis	V_OUT rising	STRICT = 1b		0.25%
	Deglitch	V_OUT falling	STRICT = 0b		1		ms
		V_OUT falling	STRICT = 1b		50		µs
		V_OUT rising	STRICT = 0b		10		µs
		V_OUT rising	STRICT = 1b		10		µs
	Time-out				5		ms
V_OV	Overvoltage detection threshold	V_OUT rising, STRICT = 1b		103%	103.5%	104%
	Hysteresis	V_OUT falling, STRICT = 1b			0.25%
	Deglitch	V_OUT rising, STRICT = 1b			50		µs
I_INRUSH	Inrush current	V_{IN_DCDC1} = 3.6 V; C_OUT = 10 µF to 100 µF				500	mA
R_DIS	Discharge resistor			150	250	350	Ω
L	Nominal inductor value	See Table 9-2.		1	1.5	2.2	µH
L	Tolerance			–30%		30%
C_OUT	Output capacitance value	Ceramic, X5R or X7R, see Table 9-3.		10	22	100⁽⁸⁾	µF
DCDC2 (1.1-V BUCK)
V_{IN_DCDC2}	Input voltage range	V_{IN_BIAS} > V_UVLO		2.7		5.5	V
V_DCDC2	Output voltage range	Adjustable through I²C		0.85		1.675	V
V_DCDC2	DC accuracy	2.7 V ≤ V_IN ≤ 5.5 V; 0 A ≤ I_OUT ≤ 1.8 A		–2%		2%
I_OUT	Continuous output current	V_{IN_DCDC2} > 2.7 V				1.8	A
I_Q	Quiescent current	Total current from I_{N_DCDC2} pin; device not switching, no load			25	50	µA
R_DS(ON)	High-side FET on resistance	V_{IN_DCDC2} = 3.6 V			230	355	mΩ
R_DS(ON)	Low-side FET on resistance	V_{IN_DCDC2} = 3.6 V			90	145	mΩ
I_LIMIT	High-side current limit	V_{IN_DCDC2} = 3.6 V			2.8		A
I_LIMIT	Low-side current limit	V_{IN_DCDC2} = 3.6 V			3.1		A
V_PG	Power-good threshold	V_OUT falling	STRICT = 0b	88.5%	90%	91.5%
	Power-good threshold	V_OUT falling	STRICT = 1b	96%	96.5%	97%
	Hysteresis	V_OUT rising	STRICT = 0b	3.8%	4.1%	4.4%
	Hysteresis	V_OUT rising	STRICT = 1b		0.25%
	Deglitch	V_OUT falling	STRICT = 0b		1		ms
		V_OUT falling	STRICT = 1b		50		µs
		V_OUT rising	STRICT = 0b		10		µs
		V_OUT rising	STRICT = 1b		10		µs
	Time-out	Occurs at enable of DCDC2 and after DCDC2 register write (register 0x17).			5		ms
V_OV	Overvoltage detection threshold	V_OUT rising, STRICT = 1b		103%	103.5%	104%
	Hysteresis	V_OUT falling, STRICT = 1b			0.25%
	Deglitch	V_OUT rising, STRICT = 1b			50		µs
I_INRUSH	Inrush current	V_{IN_DCDC2} = 3.6 V; C_OUT = 10 µF to 100 µF				500	mA
R_DIS	Discharge resistor			150	250	350	Ω
L	Nominal inductor value	See Table 9-2.		1	1.5	2.2	µH
L	Tolerance			–30%		30%
C_OUT	Output capacitance value	Ceramic, X5R or X7R, see Table 9-3.		10	22	100⁽⁸⁾	µF
DCDC3 (1.2-V BUCK)
V_{IN_DCDC3}	Input voltage range	V_{IN_BIAS} > V_UVLO		2.7		5.5	V
V_DCDC3	Output voltage range	Adjustable through I²C		0.9		3.4	V
V_DCDC3	DC accuracy	2.7 V ≤ V_IN ≤ 5.5 V; 0 A ≤ I_OUT ≤ 1.8 A, V_{IN_DCDC3} ≥ (V_DCDC3 + 700 mV)		–2%		2%
I_OUT	Continuous output current	V_{IN_DCDC3} > 2.7 V				1.8	A
I_Q	Quiescent current	Total current from IN_DCDC3 pin; Device not switching, no load			25	50	µA
R_DS(ON)	High-side FET on resistance	V_{IN_DCDC3} = 3.6 V			230	345	mΩ
R_DS(ON)	Low-side FET on resistance	V_{IN_DCDC3} = 3.6 V			100	150	mΩ
I_LIMIT	High-side current limit	V_{IN_DCDC3} = 3.6 V			2.8		A
I_LIMIT	Low-side current limit	V_{IN_DCDC3} = 3.6 V			3		A
V_PG	Power-good threshold	V_OUT falling	STRICT = 0b	88.5%	90%	91.5%
	Power-good threshold	V_OUT falling	STRICT = 1b	95%	95.5%	96%
	Hysteresis	V_OUT rising	STRICT = 0b	3.8%	4.1%	4.4%
	Hysteresis	V_OUT rising	STRICT = 1b		0.25%
	Deglitch	V_OUT falling	STRICT = 0b		1		ms
		V_OUT falling	STRICT = 1b		50		µs
		V_OUT rising	STRICT = 0b		10		µs
		V_OUT rising	STRICT = 1b		10		µs
	Time-out	Occurs at enable of DCDC3 and after DCDC3 register write (register 0x18).			5		ms
V_OV	Overvoltage detection threshold	V_OUT rising, STRICT = 1b		104%	104.5%	105%
	Hysteresis	V_OUT falling, STRICT = 1b			0.25%
	Deglitch	V_OUT rising, STRICT = 1b			50		µs
I_INRUSH	Inrush current	V_{IN_DCDC3} = 3.6 V; C_OUT = 10 µF to 100 µF				500	mA
R_DIS	Discharge resistor			150	250	350	Ω
L	Nominal inductor value	See Table 9-2.		1.0	1.5	2.2	µH
L	Tolerance			–30%		30%
C_OUT	Output capacitance value	Ceramic, X5R or X7R, see Table 9-3.		10	22	100	µF
DCDC4 (3.3-V BUCK-BOOST) / ANALOG AND I/O
	Output voltage ripple	PFM mode enabled; 4.2 V ≤ V_IN ≤ 5.5 V; 0 A ≤ I_OUT ≤ 1.6 A V_OUT = 3.3 V				150	mV_pp
	Minimum duty cycle in step-down mode					18%
I_OUT	Continuous output current	V_{IN_DCDC4} = 2.8 V, V_OUT = 3.3 V				1	A
		V_{IN_DCDC4} = 3.6 V, V_OUT = 3.3 V				1.3
		V_{IN_DCDC4} = 5 V, V_OUT = 3.3 V				1.6
I_Q	Quiescent current	Total current from IN_DCDC4 pin; Device not switching, no load.			25	50	µA
f_SW	Switching frequency				2400		kHz
R_DS(ON)	High-side FET on resistance	V_{IN_DCDC3} = 3.6 V	IN_DCDC4 to L4A		166		mΩ
	High-side FET on resistance	V_{IN_DCDC3} = 3.6 V	L4B to DCDC4		149
	Low-side FET on resistance	V_{IN_DCDC3} = 3.6 V	L4A to GND		142	190
	Low-side FET on resistance	V_{IN_DCDC3} = 3.6 V	L4B to GND		144	190
I_LIMIT	Average switch current limit	V_{IN_DCDC4} = 3.6 V			3000		mA
V_PG	Power-good threshold	V_OUT falling	STRICT = 0b	88.5%	90%	91.5%
	Power-good threshold	V_OUT falling	STRICT = 1b	95%	95.5%	96%
	Hysteresis	V_OUT rising	STRICT = 0b	3.8%	4.1%	4.4%
	Hysteresis	V_OUT rising	STRICT = 1b		0.25%
	Deglitch	V_OUT falling	STRICT = 0b		1		ms
		V_OUT falling	STRICT = 1b		50		µs
		V_OUT rising	STRICT = 0b		10		µs
		V_OUT rising	STRICT = 1b		10		µs
	Time-out	Occurs at enable of DCDC4 and after DCDC4 register write (register 0x19)			5		ms
V_OV	Overvoltage detection threshold	V_OUT rising, STRICT = 1b		104%	104.5%	105%
	Hysteresis	V_OUT falling, STRICT = 1b			0.25%
	Deglitch	V_OUT rising, STRICT = 1b			50		µs
I_INRUSH	Inrush current	V_{IN_DCDC4} = 3.3 V ≤ V_INDCDC4 ≤ 5.5 V; 40 µF ≤ C_OUT ≤ 100 µF				500	mA
R_DIS	Discharge resistor			150	250	350	Ω
L	Nominal inductor value	See Table 9-2.		1.2	1.5	2.2	µH
L	Tolerance			–30%		30%
C_OUT	Output capacitance value	Ceramic, X5R or X7R, see Table 9-3.		40	80	100	µF
DCDC5 and DCDC6 POWER PATH
V_CC	DCDC5 and DCDC6 input voltage range.	V_{IN_BU} = 0 V		2.2		3.3	V
V_{IN_BU}	DCDC5 and DCDC6 input voltage range⁽¹⁾			2.2		5.5	V
t_RISE	V_CC, V_{IN_BU} rise time	V_CC = 0 V to 3.3 V, V_{IN_BU} = 0 V to 5.5 V		30			µs
R_DS(ON)	Power path switch impedance	CC to SYS_BU V_CC = 2.4 V, V_{IN_BU} = 0 V			14.5		Ω
R_DS(ON)	Power path switch impedance	IN_BU to SYS_BU V_{IN_BU} = 3.6 V			10.5		Ω
I_LEAK	Forward leakage current	Into CC pin; V_CC = 3.3 V, V_{IN_BU} = 0 V; OFF state; FSEAL = 0b; over full temperature range			50	300	nA
I_LEAK	Reverse leakage current	Out of CC pin; V_CC = 1.5 V; V_{IN_BU} = 5.5 V; over full temperature range				500	nA
R_CC	Acceptable CC source impedance	I_{OUT, DCDC5} < 10 µA; I_{OUT, DCDC6} < 10 µA				1000	Ω
IQ	Quiescent current	Average current into CC pin; RECOVERY or OFF state; V_{IN_BU} = 0 V; V_CC = 2.4 V; DCDC5 and DCDC6 enabled, no load T_J = 25°C			350		nA
Q_INRUSH	Inrush charge	V_{IN_BIAS} = decaying; CC = 3 V; C_{SYS_BU} = 1 µF; SYS_BU = 2.3 V to 3 V; CC_{series_resist} = 10 Ω C_CC = 4.7 µF			720		nC
DCDC5 (1-V BATTERY BACKUP SUPPLY)
V_DCDC5	Output voltage				1		V
	DC accuracy	2.7 V ≤ V_{IN_BU} ≤ 5.5 V; 1.5 µA ≤ I_OUT ≤ 25 mA –40°C ≤ T_A < 0°C		–2.5%		2.5%
		2.7 V ≤ V_{IN_BU} ≤ 5.5 V 1.5 µA ≤ I_OUT ≤ 25 mA 0°C ≤ T_A < 105°C		–2%		2%
		2.2 V ≤ V_CC ≤ 3.3 V; V_{IN_BU} = 0; 1.5 µA ≤ I_OUT ≤ 100 µA		–2.5%		2.5%
	Output voltage ripple	L = 10 µH; C_OUT = 22 µF; 100-µA load, occurs during band-gap sampling				32⁽⁹⁾	mV_pp
I_OUT	Continuous output current	2.2 V ≤ V_CC ≤ 3.3 V V_{IN_BU} = 0 V			10	100	µA
I_OUT	Continuous output current	2.7 V ≤ V_{IN_BU} ≤ 5.5 V				25	mA
R_DS(ON)	High-side FET on resistance	V_{IN_BU} = 2.8 V			2.5	3.5	Ω
R_DS(ON)	Low-side FET on resistance	V_{IN_BU} = 2.8 V			2	3	Ω
I_LIMIT	High-side current limit	V_{IN_BU} = 2.8 V			50		mA
V_PG	Power-good threshold	V_OUT falling		79%	85%	91%
V_PG	Hysteresis	V_OUT rising			6%
L	Nominal inductor value	Chip inductor, see Table 9-3.		4.7	10	22	µH
L	Tolerance			–30%		30%
C_OUT	Output capacitance value	Ceramic, X5R or X7R, see Table 9-3.		20⁽¹⁰⁾		47	µF
C_OUT	Tolerance			–20%		20%
DCDC6 (1.8-V BATTERY BACKUP SUPPLY)
V_DCDC6	Output voltage				1.8		V
V_DCDC6	Output voltage ripple	L = 10 µH; C_OUT = 22 µF; 100-µA load				30⁽⁹⁾	mV_pp
I_OUT	Continuous output current	2.2 V ≤ V_CC ≤ 3.3 V V_{IN_BU} = 0 V			10	100	µA
I_OUT	Continuous output current	2.7 V ≤ V_{IN_BU} ≤ 5.5 V				25	mA
R_DS(ON)	High-side FET on resistance	V_{IN_BU} = 3 V			2.5	3.5	Ω
R_DS(ON)	Low-side FET on resistance	V_{IN_BU} = 3 V			2	3	Ω
I_LIMIT	High-side current limit	V_{IN_BU} = 3 V			50		mA
V_PG	Power-good threshold	V_OUT falling		87%	91%	95%
V_PG	Hysteresis	V_OUT rising			3%
L	Nominal inductor value	Chip inductor, see Table 9-3		4.7	10	22	µH
L	Tolerance			–30%		30%
C_OUT	Output capacitance value	Ceramic, X5R or X7R, see Table 9-3		20⁽¹⁰⁾		47	µF
C_OUT	Tolerance			–20%		20%
LDO1 (1.8-V LDO)
V_{IN_LDO1}	Input voltage range	V_{IN_BIAS} > V_UVLO		1.8		5.5	V
I_Q	Quiescent current	No load			35		µA
V_OUT	Output voltage range	Adjustable through I²C		0.9		3.4	V
V_OUT	DC accuracy	V_OUT + 0.2 V ≤ V_IN ≤ 5.5 V; 0 A ≤ I_OUT ≤ 200 mA		–2%		2%
I_OUT	Output current range	V_{IN_LDO1} – V_DO = V_OUT		0		200	mA
I_OUT	Output current range	V_{IN_LDO1} > 2.7 V, V_OUT = 1.8 V		0		400	mA
I_LIMIT	Short circuit current limit	Output shorted to GND		445	550		mA
V_DO	Dropout voltage	I_OUT = 100 mA, V_IN = 3.6 V				200	mV
V_PG	Power-good threshold	V_OUT falling	STRICT = 0b	86%	90%	94%
		V_OUT falling	STRICT = 1b	95%	95.5%	96%
		Hysteresis, V_OUT rising	STRICT = 0b	3%	4%	5%
		Hysteresis, V_OUT rising	STRICT = 1b		0.25%
	Deglitch	V_OUT falling	STRICT = 0b		1		ms
		V_OUT falling	STRICT = 1b		50		µs
		V_OUT rising	STRICT = 0b		10		µs
		V_OUT rising	STRICT = 1b		10		µs
	Time-out	Occurs at enable of LDO and after LDO register write (register 0x1B)			5		ms
V_OV	Overvoltage detection threshold	V_OUT rising, STRICT = 1b		104%	104.5%	105%
	Hysteresis	V_OUT falling, STRICT = 1b			0.25%
	Deglitch	V_OUT rising, STRICT = 1b			50		µs
	Deglitch	V_OUT falling, STRICT = 1b			1		ms
R_DIS	Discharge resistor			150	250	380	Ω
C_OUT	Output capacitance value	Ceramic, X5R or X7R			22	100	µF
LOAD SWITCH 1 (LS1)
V_{IN_LS1}	Input voltage range	V_{IN_BIAS} > V_UVLO		1.2		3.6	V
R_DS(ON)	Static on resistance	V_{IN_LS1} = 3.3 V, I_OUT = 300 mA, over full temperature range				110	mΩ
		V_{IN_LS1} = 1.8 V, I_OUT = 300 mA, DDR2, LPDDR, MDDR at 266 MHz over full temperature range				110
		V_{IN_LS1} = 1.5 V, I_OUT = 300 mA, DDR3 at 333 MHz over full temperature range				110
		V_{IN_LS1} = 1.35 V, I_OUT = 300 mA, DDR3L at 333 MHz over full temperature range				110
		V_{IN_LS1} = 1.2 V, I_OUT = 200 mA, LPDDR2 at 333 MHz over full temperature range				150
I_LIMIT	Short circuit current limit	Output shorted to GND		350			mA
t_BLANK	Interrupt blanking time	Output shorted to GND until interrupt is triggered.			15		ms
R_DIS	Internal discharge resistor at output⁽²⁾	LS1DCHRG = 1		150	250	380	Ω
T_OTS	Overtemperature shutdown⁽³⁾			125	132	139	°C
T_OTS	Hysteresis				10		°C
C_OUT	Nominal output capacitance value	Ceramic, X5R or X7R, see Table 9-3.		10		100	µF
LOAD SWITCH 2 (LS2)
V_{IN_LS2}	Input voltage range	V_{IN_BIAS} > V_UVLO		3		5.5	V
V_UVLO	Undervoltage lockout	Measured at IN_LS2. Supply falling⁽⁴⁾		2.48	2.6	2.7	V
V_UVLO	Hysteresis	Input voltage rising			170		mV
R_DS(ON)	Static on resistance	V_{IN_LS2} = 5 V, I_OUT = 500 mA, over full temperature range				500	mΩ
I_LIMIT	Short circuit current limit	Output shorted to GND; V_{IN_LS2} ≥ 4 V	LS2ILIM[1:0] = 00b	94		126	mA
			LS2ILIM[1:0] = 01b	188		251
			LS2ILIM[1:0] = 10b	465		631
			LS2ILIM[1:0] = 11b	922		1290
I_LEAK	Reverse leakage current	V_LS2 > V_{IN_LS2} + 1 V			12	30	µA
t_BLANK	Interrupt blanking time	Output shorted to GND until interrupt is triggered			15		ms
R_DIS	Internal discharge resistor at output⁽²⁾	LS2DCHRG = 1b		150	250	380	Ω
T_OTS	Overtemperature shutdown⁽⁴⁾			125	132	139	°C
T_OTS	Hysteresis				10		°C
C_OUT	Nominal output capacitance value	Ceramic, X5R or X7R, see Table 9-3.		1		100	µF
LOAD SWITCH 3 (LS3)
V_{IN_LS3}	Input voltage range	V_{IN_BIAS} > V_UVLO		1.8		10	V
R_DS(ON)	Static on resistance	V_{IN_LS3} = 9 V, I_OUT= 500 mA, over full temperature range				440	mΩ
		V_{IN_LS3} = 5 V, I_OUT= 500 mA, over full temperature range				526
		V_{IN_LS3} = 2.8 V, I_OUT= 200 mA, over full temperature range				656
		V_{IN_LS3} = 1.8 V, I_OUT= 200 mA, over full temperature range				910
I_LIMIT	Short circuit current limit	V_{IN_LS3} > 2.3 V, Output shorted to GND	LS3ILIM[1:0] = 00b	98		126	mA
			LS3ILIM[1:0] = 01b	194		253
			LS3ILIM[1:0] = 10b	475		738
			LS3ILIM[1:0] = 11b	900		1234
		V_{IN_LS3} ≤ 2.3 V, Output shorted to GND	LS3ILIM[1:0] = 00b	98		126
			LS3ILIM[1:0] = 01b	194		253
			LS3ILIM[1:0] = 10b	475		738
t_BLANK	Interrupt blanking time	Output shorted to GND until interrupt is triggered.			15		ms
R_DIS	Internal discharge resistor at output⁽²⁾	LS3DCHRG = 1		650	1000	1500	Ω
T_OTS	Overtemperature shutdown⁽⁴⁾			125	132	139	°C
T_OTS	Hysteresis				10		°C
C_OUT	Nominal output capacitance value	Ceramic, X5R or X7R, see Table 9-3.		1	100	220	µF
BACKUP BATTERY MONITOR
V_TH	Comparator threshold	Ideal level			3		V
		Good level			2.6		V
		Low level			2.3		V
	Accuracy			–3%		3%
R_LOAD	Load impedance	Applied from CC to GND during comparison.		70	100	130	kΩ
t_DLY	Measurement delay	R_LOAD is connected during delay time. Measurement is taken at the end of delay.			600		ms
I/O LEVELS AND TIMING CHARACTERISTICS
PG_DLY	PGOOD delay time	PGDLY[1:0] = 00b			10		ms
		PGDLY[1:0] = 01b			20
		PGDLY[1:0] = 10b			50
		PGDLY[1:0] = 11b			150
t_DG	Deglitch time	PB input	Rising edge		100		ms
		PB input	Falling edge		50		ms
		AC_DET input	Rising edge		100		µs
		AC_DET input	Falling edge		10		ms
		PWR_EN input	Rising edge		10		ms
		PWR_EN input	Falling edge		100		µs
		GPIO1	Rising edge		1		ms
		GPIO1	Falling edge		1		ms
		GPIO3	Rising edge		5		µs
		GPIO3	Falling edge		5		µs
t_RESET	Reset time	PB input held low	TRST = 0b		8		s
t_RESET	Reset time	PB input held low	TRST = 1b		15		s
V_IH	High level input voltage	SCL, SDA, GPIO1, and GPIO3		1.3			V
		AC_DET, PB		0.66 × IN_BIAS
		PWR_EN		1.3
V_IL	Low level input voltage	SCL, SDA, PWR_EN, AC_DET, PB, GPIO1, and GPIO3		0		0.4	V
V_OH	High level output voltage	GPO2; I_SOURCE = 5 mA; GPO2_BUF = 1		V_{IN_LS1} – 0.3		V_{IN_LS1}	V
V_OH	High level output voltage	PGOOD_BU; I_SOURCE = 100 µA		V_DCDC6 – 10 mV			V
V_OL	Low level output voltage	nWAKEUP, nINT, SDA, PGOOD, GPIO1, GPO2, and GPIO3; I_SINK = 2 mA		0		0.3	V
		nPFO; I_SINK = 2 mA		0		0.35
		PGOOD_BU; I_SINK = 100 µA		0		0.3
V_PFI	Power-fail comparator threshold	Input falling			800		mV
	Hysteresis	Input rising			40		mV
	Accuracy			–4%		4%
	Deglitch	Input falling			25		µs
	Deglitch	Input rising			10		ms
I_{DC34_SEL}	DC34_SEL bias current	Enabled only at power-up.		9.05	10	11.93	µA
V_{DC34_SEL}	DCDC3 and DCDC4 power-up default selection thresholds	Threshold 1			100		mV
		Threshold 2			163
		Threshold 3			275
		Threshold 4			400
		Threshold 5			575
		Threshold 6			825
		Threshold 7			1200
R_{DC34_SEL}	DCDC3 and DCDC4 power-up default selection resistor values	Setting 0		0	0	7.7	kΩ
		Setting 1		11.8	12.1	12.4
		Setting 2		19.5	20	20.5
		Setting 3		30.9	31.6	32.3
		Setting 4		44.4	45.3	46.3
		Setting 5		64.8	66.1	67.3
		Setting 6		93.6	95.3	97.2
		Setting 7		146	150
I_BIAS	Input bias current	SCL, SDA, GPIO1⁽⁵⁾, GPIO3⁽⁵⁾; V_IN = 3.3 V			0.01	1	µA
I_BIAS	Input bias current	PB, AC_DET, PFI; V_IN = 3.3 V				500	nA
I_LEAK	Pin leakage current	nINT, nWAKEUP, nPFO, PGOOD, PWR_EN, GPIO1⁽⁶⁾, GPO2⁽⁷⁾, GPIO3⁽⁶⁾ V_OUT = 3.3 V				500	nA
OSCILLATOR
ƒ_OSC	Oscillator frequency				2400		kHz
ƒ_OSC	Frequency accuracy	T_J = –40°C to +105°C		–12%		12%
OVERTEMPERATURE SHUTDOWN
T_OTS	Overtemperature shutdown	Increasing junction temperature		135	145	155	°C
T_OTS	Hysteresis	Decreasing junction temperature			20		°C
T_WARN	High-temperature warning	Increasing junction temperature		90	100	110	°C
T_WARN	Hysteresis	Decreasing junction temperature			15		°C

(1) IN_BU has priority over CC input.

(2) Discharge function disabled by default.

(3) Switch is temporarily turned OFF if temperature exceeds OTS threshold.

(4) Switch is temporarily turned OFF if input voltage drops below UVLO threshold.

(5) Configured as input.

(6) Configured as output.

(7) Configured as open-drain output.

(8) 500-µF of remote capacitance can be supported for DCDC1 and DCDC2.

(9) For PHP package: 160 mVpp at -40°C, and 120 mVpp from 25°C to 105°C.

(10) For PHP package: 40 µF.