SLVSGA0B May 2022 – June 2024 TPS65219
PRODUCTION DATA
An OFF-request or a shut-down-fault triggers the power-down sequence. The OFF-request can be triggered by a falling edge on EN/PB/VSENSE if configured for EN or VSENSE respectively a long press of the push-button if configured as PB or by an I2C-command to I2C_OFF_REQ in MFP_CTRL register. This bit self-clears.
An I2C-triggered shut-down requires a renewed ON-request on the EN/PB/VSENSE pin. In case of EN- or VSENSE-configuration, a low-going edge followed by a high-going-edge is required on the EN/PB/VSENSE-pin. The falling-edge deglitch time for EN or VSENSE configuration tDEGL_EN/VSENSE_I2C is shorter than the deglitch-time for pin-induced OFF-requests (tDEGL_EN_Fall and tDEGL_VSENSE_Fall). The deglitch-times for PB-configuration remain.
In many cases, the power-down sequence follows the reverse power-up sequence. In some applications, all rails can be required to shut down at the same time with no delay between rails or require wait-times to allow discharging of rail.
The power-down sequence is configured as follows:
Active discharge is enabled by default and not NVM based. Thus, if desired, discharge need to be disabled after each VSYS-power-cycle. During RESET or OFF-request, the discharge configuration is not reset, as long as VSYS is present. However, in INITIALIZE state and prior to the power-up-sequence, all rails get discharged, regardless of the setting.
During the power-down-sequence, non-EEPROM-backed bits get reset, with the exception of unmasked interrupt bits and *_DISCHARGE_EN bits.
Below graphic shows the power-down-sequence for NVM-ID 0x01, revision 0x2 as an example:
Non-NVM-bits are not accessible for approximately 80 μs after starting a transition into INITIALIZE state.