SLVSGZ4A June 2023 – June 2024 TPS6521905
PRODUCTION DATA
In this example, a single TPS6521905 PMIC is used to power a generic processor. This power distribution network (PDN) shows a 3.3V input supply but 5V can be used as well to supply the Bucks and LDO (if not configured as bypass). To reduce power dissipation, the output from one of the PMIC Buck regulators can be used to supply the LDOs if it meets the required headroom and sequence needs. For example, Buck2 (1.8V) is used to supply LDO2 (0.85V). LDO1 is configured as bypass and assigned to supply the SD card interface. The bypass mode allows voltage change between VSET_LDO1 and 1.8V to meet the SD spec for UHS speed which requires 3.3V to initialize the card before the voltage can be lowered to 1.8V for faster rise/fall time and lower electromagnetic interference. The VSEL_SD multifunction pin can be configured to trigger the voltage change during operation. Since Buck1 is the regulator with the highest current capabilities, it was assigned to supply the CORE rail of the processor. Each of the Buck regulators have the option to be configured for high bandwidth to support higher load transients and higher total capacitance (local + point of load). Since the PMIC is being supplied by a 3.3V rail, an external load switch is used to supply the 3.3V IO domain on the processor. One of the PMIC GPOs (GPO2) is configured to be part of the power-up/power-down sequence and enables the external power-switch.