SLVSGZ4A June 2023 – June 2024 TPS6521905
PRODUCTION DATA
POS | MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|---|
3.1.1 | VVSYS | Input voltage | 2.5 (1) | 5.5 | V | |
3.1.2 | VPVIN_B1, VPVIN_B2, VPVIN_B3 VLX_B1, VLX_B2, VLX_B3 |
BUCKx Pins | 2.5 | 5.5 (2) | V | |
3.1.3 | ΔVVSYS_PVIN_Bx | Voltage by which VPVIN_Bx may exceed VVSYS | 0 | mV | ||
3.1.4 | ΔVVSYS_PVIN_LDO1,LDO2 | Voltage by which VPVIN_LDO1 or VPVIN_LDO2 may exceed VVSYS | 0 | mV | ||
3.1.5 | ΔVVSYS_VLDO34 | Voltage by which VVSYS must exceed LDO output voltage (VLDO3, VLDO4); VVSYS = 2.5V to 3.45V; LDO mode | 150 | mV | ||
3.1.6 | ΔVVSYS_VLDO34 | Voltage by which VVSYS must exceed LDO output voltage (VLDO3, VLDO4); VVSYS = 3.45V to 5.5V in LDO-mode or VVSYS = 2.5V to 5.5V in LSW-mode | n/a | mV | ||
3.1.7 | CPVIN_B1, CPVIN_B2, CPVIN_B3 |
BUCKx Input Capacitance | 3.9 | 4.7 | µF | |
3.1.8 | LB1, LB2, LB3 | BUCKx Output Inductance | 330 | 470 | 611 | nH |
3.1.9a | COUT_B1, COUT_B2, COUT_B3 |
BUCKx Output Capacitance, forced PWM or auto-PFM, low bandwidth case | 10 | 75 | µF | |
3.1.10a | COUT_B1, COUT_B2, COUT_B3 |
BUCKx Output Capacitance, forced PWM or auto-PFM, high bandwidth case | 30 | 220 | µF | |
3.1.11 | VFB_B1, VFB_B2, VFB_B3 |
BUCKx FB Pins | 0 | 5.5 (2) | V | |
3.1.12 | VPVIN_LDO1, VPVIN_LDO2 | LDO Input Voltage | 1.5 | 5.5 (2) | V | |
3.1.13 | VPVIN_LDO1, VPVIN_LDO2 | LDO Input Voltage in bypass mode | 1.5 | 3.6 | V | |
3.1.14 | VPVIN_LDO1, VPVIN_LDO2 | Allowable delta between VPVIN_LDOx and configured VVLDOx in bypass mode | -200 | 200 | mV | |
3.1.15 | VVLDO1, VVLDO2 | LDO Output Voltage Range | 0.6 | 3.4 | V | |
3.1.16 | CPVIN_LDO1, CPVIN_LDO2 | LDO Input Capacitance | 1.6 | 2.2 | µF | |
3.1.17 | CVLDO1, CVLDO2 | LDO Output Capacitance | 1.6 | 2.2 | 20 | µF |
3.1.18 | VPVIN_LDO3, VPVIN_LDO4 | LDO Input Voltage | 2.2 | 5.5 (2) | V | |
3.1.19 | VVLDO3, VVLDO4 | LDO Output Voltage Range | 1.2 | 3.3 | V | |
3.1.20 | CPVIN_LDO34 | LDO Input Capacitance | 2.2 | 4.7 | µF | |
3.1.21 | CVLDO3, CVLDO4 | LDO Output Capacitance | 1.6 | 2.2 | 30 (3) | µF |
3.1.22 | VVDD1P8 | VDD1P8 pin | 0 | 1.8 | V | |
3.1.23 | CVDD1P8 | Internal Regulator Decoupling Capacitance | 1 | 2.2 | 4 | µF |
3.1.24 | CVSYS | VSYS Input Decoupling Capacitance | 1 | 2.2 | µF | |
3.1.25 | VnINT, VnRSTOUT | Digital Outputs | 0 | 3.4 | V | |
3.1.26 | VGPO1, VGPO2, VGPIO | Digital Outputs | 0 | 5.5 (2) | V | |
3.1.27 | VSCL, VSDA | I2C Interface | 0 | 3.4 | V | |
3.1.28 | VEN/PB/VSENSE, VMODE/STBY, VMODE/RESET, VVSEL_SD/VSEL/DDR |
Digital Inputs | 0 | 5.5 (2) | V | |
3.2.1 | tVSYS_RAMP_RISE | Input voltage rising ramp Time, Input voltage controlled by a pre-regulator. VVSYS = VPVIN_Bx = VPVIN_LDOx = 0V to 5V |
0.1 | 600000 | ms | |
3.2.2 | tVSYS_RAMP_FALL | Input voltage falling Ramp Time, VVSYS = VPVIN_Bx = VPVIN_LDOx = 5V to 2.5V | 0.4 | 600000 | ms | |
3.3.1 | TA | Operating free-air temperature | –40 | 105 | °C | |
3.3.2 | TJ | Operating junction temperature | –40 | 125 | °C |