SLVSGZ4A June   2023  – June 2024 TPS6521905

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  System Control Thresholds
    6. 5.6  BUCK1 Converter
    7. 5.7  BUCK2, BUCK3 Converter
    8. 5.8  General Purpose LDOs (LDO1, LDO2)
    9. 5.9  General Purpose LDOs (LDO3, LDO4)
    10. 5.10 GPIOs and multi-function pins (EN/PB/VSENSE, nRSTOUT, nINT, GPO1, GPO2, GPIO, MODE/RESET, MODE/STBY, VSEL_SD/VSEL_DDR)
    11. 5.11 Voltage and Temperature Monitors
    12. 5.12 I2C Interface
    13. 5.13 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Power-Up Sequencing
      2. 6.3.2  Power-Down Sequencing
      3. 6.3.3  Push Button and Enable Input (EN/PB/VSENSE)
      4. 6.3.4  Reset to SoC (nRSTOUT)
      5. 6.3.5  Buck Converters (Buck1, Buck2, and Buck3)
      6. 6.3.6  Linear Regulators (LDO1 through LDO4)
      7. 6.3.7  Interrupt Pin (nINT)
      8. 6.3.8  PWM/PFM and Low Power Modes (MODE/STBY)
      9. 6.3.9  PWM/PFM and Reset (MODE/RESET)
      10. 6.3.10 Voltage Select pin (VSEL_SD/VSEL_DDR)
      11. 6.3.11 General Purpose Inputs or Outputs (GPO1, GPO2, and GPIO)
      12. 6.3.12 I2C-Compatible Interface
        1. 6.3.12.1 Data Validity
        2. 6.3.12.2 Start and Stop Conditions
        3. 6.3.12.3 Transferring Data
    4. 6.4 Device Functional Modes
      1. 6.4.1 Modes of Operation
        1. 6.4.1.1 OFF State
        2. 6.4.1.2 INITIALIZE State
        3. 6.4.1.3 ACTIVE State
        4. 6.4.1.4 STBY State
        5. 6.4.1.5 Fault Handling
    5. 6.5 Multi-PMIC Operation
    6. 6.6 NVM Programming
      1. 6.6.1 TPS6521905 default NVM settings
      2. 6.6.2 NVM programming in Initialize State
      3. 6.6.3 NVM Programming in Active State
    7. 6.7 User Registers
    8. 6.8 Device Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Typical Application Example
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1 Buck1, Buck2, Buck3 Design Procedure
        2. 7.2.3.2 LDO1, LDO2 Design Procedure
        3. 7.2.3.3 LDO3, LDO4 Design Procedure
        4. 7.2.3.4 VSYS, VDD1P8
        5. 7.2.3.5 Digital Signals Design Procedure
      4. 7.2.4 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.7 BUCK2, BUCK3 Converter

over operating free-air temperature range (unless otherwise noted)
POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Electrical Characteristics
6.1.1a VIN_BUCK23 Input Voltage(1) Buck supply voltage, maximum VSYS 2.5 5.5 V
6.1.1b VOUT_BUCK23 Buck Output Voltage configurable Range Output voltage configurable in 25mV-steps for 0.6V ≤ VOUT ≤ 1.4V, in 100mV steps for 1.4V < VOUT ≤ 3.4V 0.6 3.4 V
6.1.2a IQ_BUCK23 Quiescent Current at 25°C, PFM PFM, BUCKx enabled, no load,
VIN = 5.0V, VOUT = 1.2V, TJ=25°C		 10 13 μA
6.1.2b IQ_BUCK23 Quiescent Current -40°C to 125°C, PFM, low BW case PFM, BUCKx enabled, no load,
VIN = 5.0V, VOUT = 1.2V, TJ=-40°C to 125°C		 15 43 μA
6.1.2c IQ_BUCK23
Quiescent Current -40°C to 150°C, PFM, low BW case
 		 PFM, BUCKx enabled, no load,
VIN = 5.0V, VOUT = 1.2V, TJ=-40°C to 150°C		 20 63 μA
6.1.3a VHEADROOM_PWM Input to Output Voltage Headroom(2) Corner cases at maximum load IOUT = 65% of IOUT_MAX  
 500 mV
6.1.3b VHEADROOM_PWM Input to Output Voltage Headroom at IOUT = IOUT_MAX(2) Corner cases at IOUT = IOUT_MAX
 700 mV
6.1.4 VOUT_STEP_LOW Output voltage Steps Buck2 and Buck3 0.6V ≤ VOUT ≤ 1.4V 25 mV
6.1.5 VOUT_STEP_HIGH Output voltage Steps Buck2, Buck3 1.5V ≤ VOUT ≤ 3.4V 100 mV
6.1.6a VOUT_ACC_DC_PWM DC Output Voltage Accuracy in forced PWM mode, low and high BW case IOUT = IOUT_MAX,
VOUT ≥ 0.7V to 3.4V,
VIN - VOUT > 700 mV
forced PWM, low BW case		 –1.5% 1.5%
6.1.6b VOUT_ACC_DC_PWM DC Output Voltage Accuracy in forced PWM mode, low and high BW case IOUT = IOUT_MAX,
VOUT = 0.6V to 0.7V,
VIN - VOUT > 700 mV
forced PWM, low BW case		 –10 10 mV
6.1.6c VOUT_ACC_DC_PFM DC Output Voltage Accuracy in auto-PFM mode, low and high BW case IOUT = 1mA,
VOUT = 0.6V to 3.4V,
VIN - VOUT > 500 mV
auto-PFM, low BW case		 –3.0% 3.5%
6.1.9 RFB_INPUT Feedback input impedance Converter enabled 2.3 3.75 5.0 MΩ
6.2.1a VLOAD_REG_PWM DC Load Regulation, forced PWM, low BW case VIN = 5.0V, VOUT = 1.2V,
IOUT = 0 to IOUT_MAX,
forced PWM, low BW case		 0.1 0.16 %/A
6.2.2a VLINE_REG DC Line Regulation, forced PWM, low BW case VIN = 3.3V to 5.5V,
VOUT = 1.2V,
IOUT = 1mA and IOUT_MAX
forced PWM, low BW case, COUT = 40μF		 0.1 0.16 %/V
6.2.3a VLOAD_TRANSIENT Load Transient, VOUT=0.75V, auto-PFM, high BW case VIN = 5.0V, VOUT = 0.75V,
IOUT = 100mA to 1100mA to 100mA,
tR = tF = 500ns,
auto-PFM, high BW case, COUT = 80μF		 –27.5 27.5 mV
6.2.3b VLOAD_TRANSIENT Load Transient, VOUT=0.75V, forced PWM, high BW case VIN = 5.0V, VOUT = 0.75V,
IOUT = 100mA to 1100mA to 100mA,
tR = tF = 500ns,
forced PWM, high BW case, COUT = 80 μF		 –27.5 27.5 mV
6.2.4a VLOAD_TRANSIENT Load Transient, VOUT=1.8V, auto-PFM, low BW case VIN = 5.0V, VOUT = 1.8V,
IOUT = 1mA to 1A to 1mA,
tR = tF = 1μs,
auto-PFM, COUT = 40μF		 -90 90 mV
6.2.4b VLOAD_TRANSIENT Load Transient, VOUT=1.8V, forced PWM, low BW case VIN = 5.0V, VOUT = 1.8V,
IOUT = 1mA to 1A to 1mA,
tR = tF = 1μs,
forced PWM, COUT = 40μF		 -60 60 mV
6.2.5a VLINE_TRANSIENT Line Transient, VOUT=1.2V, forced PWM, low BW case VIN = 3.3V to 5.5V in 50μs,
VOUT = 1.2V, IOUT = 1mA and IOUT_MAX,
forced PWM, low BW case, COUT = 40μF		 –50 50 mV
6.2.6a VRIPPLE_PP_PWM Forced PWM Mode, low BW case VIN = 5.0V, VOUT = 2.5V,
forced PWM, low BW case, COUT = 40uF, X5R, ESR = 10mOhm,
L = 470nH, DCR = 50mΩ
IOUT = 1A		 10 20 mVPP
6.2.6b VRIPPLE_PP_PFM Auto PFM Mode, low BW case VIN = 5.0V, VOUT = 2.5V,
auto PFM, low BW case, COUT = 40uF, X5R, ESR = 10mOhm,
L = 470nH, DCR = 50mΩ
IOUT = 20mA		 20 40 mVPP
6.3.1 IOUT_MAX Maximum Operating Current 2.0 A
6.3.2 ICURRENT_LIMIT Peak Current Limit VIN = 2.5V to 5.5V 3.1 3.9 4.7 A
6.3.3 IREV_CUR_LIMIT Reverse Peak Current Limit VIN = 2.5V to 5.5V  –2.0 –1.5 –1.0 A
6.3.4a RDSON_HS High Side MOSFET On Resistance, 5V-supply Measured Pin to Pin, VIN = 5V 110 mΩ
6.3.4b RDSON_HS High Side MOSFET On Resistance, 3.3V-supply Measured Pin to Pin, VIN = 3.3V 135 mΩ
6.3.5a RDSON_LS Low Side MOSFET On Resistance, 5V-supply Measured Pin to Pin, VIN = 5V 110 mΩ
6.3.5b RDSON_LS Low Side MOSFET On Resistance, 3.3V-supply Measured Pin to Pin, VIN = 3.3V 130 mΩ
6.3.6 RDISCHARGE Output Discharge Resistance Active only when converter is disabled 60 125 200 Ω
6.4.1 LSW Output Inductance DCR = 50mΩ max  330 470 611 nH
6.4.2a COUT Output Capacitance in auto-PFM or forced PWM for low BW case ESR = 10mΩ max 10 75 μF
6.4.3a COUT_HIGH_BW Output Capacitance in auto-PFM or forced PWM for high BW case ESR = 10mΩ max 30 220 μF
Timing Requirements
6.5.1 tRAMP Ramp Time in quasi-fixed-frequency mode Time from enable to 98% of target value, assuming no residual voltage 0.3 1.65 ms
6.5.2a DVFS_SLOPE_
QFF		 DVFS timing requirements in forced PWM, low BW case Step-duration during DVFS voltage adjustments from 0.6V to 1.4V 2.9 3.2 3.5 mV/μs
Switching Characteristics
6.5.2c DVFS_FALL DVFS timing requirements in forced PWM, falling slope Step-duration during DVFS voltage adjustments from 1.4V to 0.6V 0.45 0.53 0.61 mV/μs
6.6.1a fSW Switching Frequency, forced PWM, high or low BW case Forced PWM, VIN = 3.3V to 5V,
VOUT = 0.8V to 1.8V,
IOUT = 1A to 1.8A 
 2.3 MHz
(1) PVIN_Bx must not exceed VSYS
(2) Refers to DC-regulation only. Transient response may require more headroom. With low headroom, the frequency variation increases for quasi-fixed frequency.