SLVSGY1B December   2022  – June 2024 TPS65220

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Thermal Information
    6. 5.6  System Control Thresholds
    7. 5.7  BUCK1 Converter
    8. 5.8  BUCK2, BUCK3 Converter
    9. 5.9  General Purpose LDOs (LDO1, LDO2)
    10. 5.10 General Purpose LDOs (LDO3, LDO4)
    11. 5.11 GPIOs and multi-function pins (EN/PB/VSENSE, nRSTOUT, nINT, GPO1, GPO2, GPIO, MODE/RESET, MODE/STBY, VSEL_SD/VSEL_DDR)
    12. 5.12 Voltage and Temperature Monitors
    13. 5.13 I2C Interface
    14. 5.14 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Power-Up Sequencing
      2. 6.3.2  Power-Down Sequencing
      3. 6.3.3  Push Button and Enable Input (EN/PB/VSENSE)
      4. 6.3.4  Reset to SoC (nRSTOUT)
      5. 6.3.5  Buck Converters (Buck1, Buck2, and Buck3)
        1. 6.3.5.1 Dual Random Spread Spectrum (DRSS)
      6. 6.3.6  Linear Regulators (LDO1 through LDO4)
      7. 6.3.7  Interrupt Pin (nINT)
      8. 6.3.8  PWM/PFM and Low Power Modes (MODE/STBY)
      9. 6.3.9  PWM/PFM and Reset (MODE/RESET)
      10. 6.3.10 Voltage Select pin (VSEL_SD/VSEL_DDR)
      11. 6.3.11 General Purpose Inputs or Outputs (GPO1, GPO2, and GPIO)
      12. 6.3.12 I2C-Compatible Interface
        1. 6.3.12.1 Data Validity
        2. 6.3.12.2 Start and Stop Conditions
        3. 6.3.12.3 Transferring Data
    4. 6.4 Device Functional Modes
      1. 6.4.1 Modes of Operation
        1. 6.4.1.1 OFF State
        2. 6.4.1.2 INITIALIZE State
        3. 6.4.1.3 ACTIVE State
        4. 6.4.1.4 STBY State
        5. 6.4.1.5 Fault Handling
    5. 6.5 Multi-PMIC Operation
    6. 6.6 User Registers
    7. 6.7 Device Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Typical Application Example
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1 Buck1, Buck2, Buck3 Design Procedure
        2. 7.2.3.2 LDO1, LDO2 Design Procedure
        3. 7.2.3.3 LDO3, LDO4 Design Procedure
        4. 7.2.3.4 VSYS, VDD1P8
        5. 7.2.3.5 Digital Signals Design Procedure
      4. 7.2.4 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The TPS65220 is a Power Management IC (PMIC) designed to supply a wide range of SoCs in both portable and stationaryautomotive applications. The device is characterized across an ambient temperature range of -40°C to +125°C, making the PMIC an excellent choice for various industrialautomotive applications. The device includes three synchronous stepdown DC-DC converters and four linear regulators.

The DC-DC converters are capable of 1x 3.5A and 2x 2 A. The converters require a small 470nH inductor, 4.7μF input capacitance, and a minimum 10μF output capacitance per rail depending on the switching mode configuration.

Two of the LDOs support output currents of 400mA at an output voltage range of 0.6V to 3.4V. These LDOs support bypass mode, acting as a load-switch, and allow voltage-changes during operation. The other two LDOs support output currents of 300mA at an output voltage range of 1.2V to 3.3V. These LDOs also support load-switch mode.

The I2C-interface, IOs, GPIOs and multi-function-pins (MFP) allow a seamless interface to a wide range of SoCs.

Package Information
PART NUMBER PACKAGE(1) PACKAGE SIZE (NOM)
TPS65220 32-pin QFN 5.00mm × 5.00mm
TPS65220 32-pin QFN - Wettable Flank 5.00mm × 5.00mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
TPS65220 Simplified application Simplified application