7.3.1 Boost Converter

The TPS65233-1 consists of an internal compensated boost converter and linear regulator. The boost converter tracks the output LNB voltage to within 800 mV even at loading 950 mA, to minimize power dissipation. Under conditions where the input voltage, VBOOST, is greater than the output voltage, VLNB, the linear regulator must drop the differential voltage. When operating in these conditions, taken care to ensure that the safe operating temperature range of the TPS65233-1 is not exceeded. The boost converter operates at 1 MHz typical. The TPS65233-1 has internal pulse-by-pulse current limiting on the boost converter and DC current limiting on the LNB output to protect the IC against short circuits. When the LNB output is shorted, the LNB output current is limited. The current limit is set by the external resistor. And the IC will be shut down if the overcurrent condition lasts for more than 4 ms, the converter enters hiccup mode and will retry startup in 128 ms. At extremely light loads, the boost converter operates in a pulse-skipping mode.

If two or more set top box LNB outputs are connected together, one output voltage could be set higher than others. The output with lower set voltage would be effectively turned off. Once the voltage drops to the set level, the LNB output with lower set output voltage will return to normal conditions.

7.3.2 Linear Regulator and Current Limit

The linear regulator is used to generate the 22-kHz tone signal by changing the reference voltage. The linear regulator features low drop out voltage to minimize power loss while keeping enough head room for the 0.68-V, 22-kHz tone. It also implements a tight current limit for over current protection. The current limit is set by an external resistor connected to the ISEL pin. The curve below shows the relationship between the current limit threshold and the resistor value.

Figure 8. Linear Regulator Current Limit vs Resistor

Equation 1.

A 280-kΩ resistor sets the current to 0.5 A. The current limit can also be set by I²C through a register.

7.3.3 Charge Pump

The charge pump circuitry generates a voltage to drive the NMOS of the linear regulator. One end the charge pump capacitor is connected to the output of the boost converter. The voltage on the charge pump capacitor is about 6.25 V.

7.3.4 Slew Rate Control

When LNB output voltage transits from 13 V to 18 V or vice versa, the capacitor at pin TCAP controls the transition time. This transition is to make sure the boost converter can follow the voltage change. Usually boost converter has low bandwidth and can’t response fast. The voltage at TCAP acts as the reference voltage of the linear regulator. The boost converter’s reference is also based on TCAP with additional fixed voltage to generate 0.8 V above the output.

The charging and discharging current is 10 µA, thus the transition time can be calculated as:

Equation 2.

A 22-nF capacitor generates a 1.1-ms transition time.

In light load conditions, when LNB output voltage is set from 18 to 13 V, the voltage might drops very slow, which might cause wrong logic detection at LNB side. The TPS65233-1 has an integrated pull down circuit to pull down the output during the transition. This ensures the voltage change can follow the voltage at TCAP. Meanwhile, when the 22-kHz tone signal is superimposing on the LNB output voltage, the pull down current can also provide a square wave instead of distorted waveforms, which could cause another detection problem.

7.3.5 Short Circuit Protection, Hiccup, and Overtemperature Protection

The LNB output limit can be set by an external resistor. When short circuit conditions occur, the output current is clamped at the current limit for 4 ms. If the condition remains, the converter will shut down for 128 ms and then try restart. This hiccup behavior prevents the IC from overheating.

The low side MOSFET of the boost converter has a current limit threshold at 3.2 A, which serves as secondary protection. If the boost converter’s peak current limit is triggered, the peak current will clamp at 3.2 A. If loading current continues to increase, output voltage starts to drop and output power drops.

Thermal shutdown prevents the chip from operating at exceedingly high temperatures. When the silicon die temperature exceeds 160°C, the output shuts down. When the temperature drops below its lower threshold, typically 140°C, the output is enabled.

When the chip is in over current protection or thermal shutdown, the I²C interface and some logic are still active. The Fault pin is pulled down to signal the processor. The Fault pin signal will remain low unless the following actions are taken:

1. If I²C interface is not used to control, Enable pin must be recycled in order to pull Fault pin back to high.
2. If I²C interface is used, the I²C master needs to read the OCP or OTP bit in the register, then the Fault pin returns to high.

7.4.1 Tone Generation

A 22-kHz tone signal is superimposed at the LNB output voltage as a carrier for DiSEqC command. This tone signal can be generated by feeding an external 22-kHz clock at the EXTM pin. It can also be generated with its internal tone generator gated by control logic. The output stage of the regulator facilitates a push-pull circuit, so even at zero loading the 22-kHz tone at the output is still clear of distortion.

There are five ways to generate the 22-kHz tone signal at the output.

In non-I²C mode, only option 1 and option 2 are supported in TPS65233-1. EXTM can be tone envelope or 22 kHz burst pulse as shown in Figure 9. Option 3 and option 4 are designed for I²C interface communication mode. In I²C communication mode, TGATE bit must be written through I²C bus. If there is no bandwidth of I²C bus to write TGATE bit, there is a supplemental option 5 to generate 22-kHz tone, as shown in Figure 10. In option 5, bit TMODE and TGATE must be set as 1.

Figure 9. Four Ways to Generate 22-kHz Tone

Figure 10. Supplemental Option for 22-kHz Tone in I²C Mode

7.4.2 Serial Interface

I²C is a 2-wire serial interface developed by Philips Semiconductor (see I²C-Bus Specification, Version 2.1, January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I²C compatible devices connect to the I²C bus through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and transmits data on the bus under control of the master device.

The TPS65233-1 device works as a slave and supports the following data transfer modes, as defined in the I²C-Bus Specification: standard mode (100 kbps), and fast mode (400 kbps). The interface adds flexibility to the power supply solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements. Register contents remain intact as long as supply voltage remains above 4.5 V (typical).

The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as F/S-mode in this document. The TPS65233-1 device supports 7-bit addressing; 10-bit addressing and general call address are not supported.

The TPS65233-1 device has a 7-bit address with the 2 LSB bits set by EN pin. Connecting EN to ground set the address 0x60H, connecting to high set the address 0x61H.

7.5.1 I²C Update Sequence

The TPS65233-1 requires a start condition, a valid I²C address, a register address byte, and a data byte for a single update. After the receipt of each byte, the TPS65233-1 device acknowledges by pulling the SDA line low during the high period of a single clock pulse. The TPS65233-1 performs an update on the falling edge of the LSB byte.

When the TPS65233-1 is disabled (EN pin tied to ground) the device can still be updated via the I²C interface.

Figure 11. I²C Write Data Format

Figure 12. I²C Read Data Format

Figure 13. Legend

Table 2. Register Map

7.6.1 Control Register 1 - Address: 0x00H

7.6.2 Control Register 2 - Address: 0x01H

Some tone detection circuits in LNB are sensitive to the position of the tone on the output voltage. The TPS65233-1 provides options to select the position by setting the TONE_POS1 and TONE_POS0 bits, as illustrated below.

Figure 14. Tone Position Programmed by TONE_POS1, TONE_POS0 Bits

In addition to programming the LDO’s current continuously via an external resistor, internal registers also provide options to program the current limit. There are four options that can be selected.

7.6.3 Status Register 1 - Address: 0x02H

The TPS65233-1 has a full range of diagnostic flags for operation and debug. If any of the flags are triggered, the FAULT pin is pulled low sending an interrupt signal to processor. The processor then can read the status register to check the error conditions. The status bits are described in the following table. Among these bits, TSD and OCP are different from the others. Once TSD and OCP are set to 1, the FAULT pin logic is latched low and the processor must reset the bits in order to release the fault conditions. Other bits change as conditions change without latch.