SLVSD66 September   2015 TPS65233-1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Boost Converter
      2. 7.3.2 Linear Regulator and Current Limit
      3. 7.3.3 Charge Pump
      4. 7.3.4 Slew Rate Control
      5. 7.3.5 Short Circuit Protection, Hiccup, and Overtemperature Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Tone Generation
      2. 7.4.2 Serial Interface
    5. 7.5 Programming
      1. 7.5.1 I2C Update Sequence
    6. 7.6 Register Map
      1. 7.6.1 Control Register 1 - Address: 0x00H
      2. 7.6.2 Control Register 2 - Address: 0x01H
      3. 7.6.3 Status Register 1 - Address: 0x02H
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Detailed Design Procedure
        1. 8.2.1.1 Capacitor Selection
      2. 8.2.2 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

RTE Package
12-Pin WQFN
Top View
TPS65233-1 po_SLVSD66.gif
Exposed pad must be soldered to PCB for optimal thermal performance.

Pin Functions

PIN DESCRIPTION
NAME NUMBER
AGND 4 Analog ground. Connect all ground pins and power pad together.
BOOST 15 Output of the boost regulator and input voltage of the internal linear regulator
EN/ADDR 7 Enable pin to enable the whole chip; pull to ground to disable output, output will be pulled to ground. For I2C interface, pulling this pin high or low gives different I2C addresses.
EXTM 12 External modulation logic input pin which activates the 22-kHz tone output, feeding signal can be 22-kHz tone or logic high or low.
FAULT 8 This pin is an open drain output pin, it goes low if any fault flag is set.
ISEL 6 Connect a resistor to this pin to set the LNB output current limit.
LX 1 Switching node of the boost converter
PGND 16 Power ground for boost converter
SCL/VADJ 9 I2C compatible clock input; if I2C function is not used, connect this pin to low set output voltage 13 V/18 V, connect to high set output voltage 13.4 V/18.6 V
SDA 10 I2C compatible bi-directional data
TCAP 5 Connect a capacitor to this pin to set the rise time and fall time of the LNB output between 13 V and 18 V.
VCC 3 Internal 6.5-V power supply bias. Connect a 1-µF ceramic capacitor from this pin to ground. When VIN is 5 V, connect VCC to VIN.
VCP 14 Gate drive supply voltage, output of charge pump, connect a capacitor between this pin to pin BOOST.
VCTRL 11 Logic control pin for 13-V or 18-V voltage selection at LNB output
VIN 2 Input of internal linear regulator
VLNB 13 Output of the LNB power supply connected to satellite receiver or switch
Thermal pad — Must be soldered to PCB for optimal thermal performance. Have thermal vias on the PCB to enhance power dissipation.