SLVSDP1F
january 2017 – may 2023
TPS65235-1
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements
6.7
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Boost Converter
7.3.2
Linear Regulator and Current Limit
7.3.3
Boost Converter Current Limit
7.3.4
Charge Pump
7.3.5
Slew Rate Control
7.3.6
Short-Circuit Protection, Hiccup, and Overtemperature Protection
7.3.7
Tone Generation
7.3.8
Tone Detection
7.3.9
Audio Noise Rejection
7.3.10
Disable and Enable
7.3.11
Component Selection
7.3.11.1
Boost Inductor
7.3.11.2
Capacitor Selection
7.3.11.3
Surge Components
7.3.11.4
Consideration for Boost Filtering and LNB Noise
7.4
Device Functional Modes
7.5
Programming
7.5.1
Serial Interface Description
7.5.2
TPS65235-1 I2C Update Sequence
7.6
Register Maps
7.6.1
Control Register 1 (address = 0x00) [reset = 0x08]
7.6.2
Control Register 2 (address = 0x01) [reset = 0x09]
7.6.3
Status Register (address = 0x02) [reset = 0x29]
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
DiSEqc1.x Support
8.2.1.1
Design Requirements
8.2.1.2
Detailed Design Procedure
8.2.1.3
Application Curves
8.2.2
DiSEqc2.x Support
8.2.2.1
Design Requirements
8.2.2.2
Detailed Design Procedure
8.2.2.3
Application Curve
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.2
Layout Example
9
Device and Documentation Support
9.1
Device Support
9.1.1
Third-Party Products Disclaimer
9.2
Documentation Support
9.2.1
Related Documentation
9.3
Receiving Notification of Documentation Updates
9.4
Support Resources
9.5
Trademarks
9.6
Electrostatic Discharge Caution
9.7
Glossary
10
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RUK|20
MPQF220D
Thermal pad, mechanical data (Package|Pins)
RUK|20
QFND191D
Orderable Information
slvsdp1f_oa
slvsdp1f_pm
8.4.2
Layout Example
Figure 8-20
Layout