SLUSDQ8D december 2019 – may 2023 TPS652353
PRODUCTION DATA
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
OUTPUT VOLTAGE | ||||||
tr, tf | 13-V to 18-V transition rising falling time | C(TCAP) = 22 nF | 2 | ms | ||
tON(min) | Minimum on time for the Low side FET | 75 | 102 | 130 | ns | |
TONE | ||||||
tr(tone) | Tone rise time | 0 mA ≤ IO ≤ 500 mA,
CO = 100 nF, Control Reg1[0] = 0b | 11 | µs | ||
0 mA ≤ IO ≤ 500 mA,
CO = 100 nF, Control Reg1[0] = 1b, and EXTM has 44-kHz input | 5.5 | µs | ||||
tf(tone) | Tone fall time | 0 mA ≤ IO ≤ 500 mA,
CO = 100 nF, Control Reg1[0] = 0b | 10.8 | µs | ||
0 mA ≤ IO ≤ 500 mA,
CO = 100 nF, Control Reg1[0] = 1b, and EXTM has 44 kHz input | 5.4 | µs | ||||
OVERCURRENT PROTECTION | ||||||
tON | Overcurrent protection ON time | TIMER = 0b | 25 | 29 | 33 | ms |
tOFF | Overcurrent protection OFF time | TIMER = 0b | 208 | 233 | 260 | ms |
I2C INTERFACE | ||||||
tBUF | Bus free time between a STOP and START condition | 1.3 | µs | |||
tHD_STA | Hold time (repeated) START condition | 0.6 | µs | |||
tSU_STO | Setup time for STOP condition | 0.6 | µs | |||
tLOW | LOW period of the SCL clock | 1 | µs | |||
tHIGH | HIGH period of the SCL clock | 0.6 | µs | |||
tSU_STA | Setup time for a repeated START condition | 0.6 | µs | |||
tSU_DAT | Data setup time | 0.1 | µs | |||
tHD_DAT | Data hold time | 0 | 0.9 | µs | ||
tRCL | Rise time of SCL signal | Capacitance of one bus line (pF) | 20 + 0.1 CB | 300 | ns | |
tRCL1 | Rise time of SCL Signal after a Repeated START condition and after an acknowledge BIT | Capacitance of one bus line (pF) | 20 + 0.1 CB | 300 | ns | |
tFCL | Fall time of SCL signal | Capacitance of one bus line (pF) | 20 + 0.1 CB | 300 | ns | |
tRDA | Rise time of SDA signal | Capacitance of one bus line (pF) | 20 + 0.1 CB | 300 | ns | |
tFDA | Fall time of SDA signal | Capacitance of one bus line (pF) | 20 + 0.1 CB | 300 | ns | |
CB | Capacitance of one bus line(SCL and SDA) | 400 | pF |