SLVSC70 Data sheet

SLVSC70B January 2015 – January 2022 TPS65251-1 , TPS65251-2 , TPS65251-3

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

RHA|40
- MPQF135D

Thermal pad, mechanical data (Package|Pins)

RHA|40
- QFND227K

Orderable Information

6.5 Electrical Characteristics

T_J = –40°C to 125°C, V_IN = 12 V, ƒ_SW = 500 Hz (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
INPUT SUPPLY UVLO AND INTERNAL SUPPLY VOLTAGE
V_IN	Input voltage range		4.5		18	V
IDD_SDN	Shutdown	EN pin = Low for all converters		175		µA
IDD_Q	Quiescent, low power disabled (Lo)	Converters enabled, no load Buck 1 = 3.3 V, Buck 2 = 2.5 V, Buck 3 = 7.5 V, L = 4.7 µH , ƒ_SW = 800 kHz		20		mA
IDD_{Q_LOW_P}	Quiescent, low power enabled (Hi)	Converters enabled, no load Buck 1 = 3.3 V, Buck 2 = 2.5 V, Buck 3 = 7.5 V, L = 4.7 µH , ƒ_SW = 800 kHz		1		mA
UVLO_VIN	V_IN undervoltage lockout	Rising V_IN		4.22		V
UVLO_VIN	V_IN undervoltage lockout	Falling V_IN		4.1		V
UVLO_DEGLITCH		Both edges		110		µs
V_3p3	Internal biasing supply			3.3		V
V_7V	Internal biasing supply			6.25		V
V7V_UVLO	UVLO for internal V7V rail	Rising V7V		3.8		V
V7V_UVLO	UVLO for internal V7V rail	Falling V7V		3.6		V
V7V_{UVLO_DEGLITCH}		Falling edge		110		µs
BUCK CONVERTERS (ENABLE CIRCUIT, CURRENT LIMIT, SOFT START, SWITCHING FREQUENCY AND SYNC CIRCUIT, LOW POWER MODE)
V_IH	Enable threshold high	External GPIO mode, V3p3 = 3.2 to 3.4 V	0.66 x V_3p3			V
V_IH	Enable high level	V3p3 = 3.2 to 3.4 V, V_ENX rising	1.55	1.67	1.82	V
V_IL	Enable threshold low	External GPIO mode, V3p3 = 3.2 to 3.4 V			0.33 x V_3p3	V
V_IL	Enable low level	V3p3 = 3.2 to 3.4 V, V_ENX falling	0.98	1.10	1.24	V
R_{EN_DIS}	Enable discharge resistor		–25%	2.1	25%	kΩ
ICH_EN	Pullup current enable pin			1.1		µA
t_D	Discharge time enable pins	Power-up		10		ms
I_SS	Soft-start pin current source			5		µA
F_{SW_BK}	Converter switching frequency range	Set externally with resistor	0.3		2.2	MHz
R_FSW	Frequency setting resistor	Depending on set frequency	50		600	kΩ
ƒ_{SW_TOL}	Internal oscillator accuracy	ƒ_SW = 800 kHz	–10%		10%
V_SYNCH	External clock threshold high	V3p3 = 3.3 V			1.24	V
V_SYNCL	External clock threshold low	V3p3 = 3.3 V	1.55			V
SYNC_RANGE	Synchronization range		0.2		2.2	MHz
SYNC_{CLK_MIN}	Sync signal minimum duty cycle		40%
SYNC_{CLK_MAX}	Sync signal maximum duty cycle				60%
VIH_{LOW_P}	Low power mode threshold high	V3p3 = 3.3 V, V_ENX rising	1.55			V
VIL_{LOW_P}	Low power mode threshold Low	V3p3 = 3.3 V, V_ENX falling			1.24	V
FEEDBACK, REGULATION, OUTPUT STAGE
V_FB	Feedback voltage	V_IN = 12 V, T_J = 25°C	–1%	0.8	1%	V
V_FB	Feedback voltage	V_IN = 4.5 to 18 V	–2%	0.8	2%	V
I_FB	Feedback leakage current				50	nA
t_{ON_MIN}	Minimum on-time (current sense blanking) to specify output regulation			70	100	ns
RLIM₁	Limit resistance range	V_IN = 12 V, ƒ_SW = 500 kHz	75		300	kΩ
RLIM_2,3	Limit resistance range	V_IN = 12 V, ƒ_SW = 500 kHz	1.1		5.1	A
ILIM₁	Buck1 current limit range	V_IN = 12 V, ƒ_SW = 500 kHz	100		300	kΩ
ILIM₂	Buck2 current limit range	V_IN = 12 V, ƒ_SW = 500 kHz	1.2		4.1	A
ILIM₃	Buck3 current limit range	V_IN = 12 V, ƒ_SW = 500 kHz	1.2		4.1	A
MOSFET (BUCK 1)
H.S. Switch	Turn-on resistance high-side FET on CH1	BOOT = 6.5 V, T_J = 25°C		95		mΩ
L.S. Switch	Turn-on resistance low-side FET on CH1	V_IN = 12 V, T_J = 25°C		50		mΩ
MOSFET (BUCK 2)
H.S. Switch	Turn-on resistance high-side FET on CH2	BOOT = 6.5 V, T_J = 25°C		120		mΩ
L.S. Switch	Turn-on resistance low-side FET on CH2	V_IN = 12 V, T_J = 25°C		80		mΩ
MOSFET (BUCK 3)
H.S. Switch	Turn-on resistance high-side FET on CH3	BOOT = 6.5 V, T_J = 25°C		120		mΩ
L.S. Switch	Turn-on resistance low-side FET on CH3	V_IN = 12 V, T_J = 25°C		80		mΩ
ERROR AMPLIFIER
g_M	Error amplifier transconductance	–2 µA < I_COMP < 2 µA		130		µmhos
gm_PS	COMP to ILX g_M	ILX = 0.5 A		10		A/V
POWER GOOD RESET GENERATOR
VUV_BUCKX	Threshold voltage for buck under voltage	Output falling		85%
VUV_BUCKX	Threshold voltage for buck under voltage	Output rising (PG is asserted)		90%
t_{UV_deglitch}	Deglitch time (both edges)	Each buck		11		ms
t_{ON_HICCUP}	Hiccup mode ON time	VUV_BUCKX asserted		13		ms
t_{OFF_HICCUP}	Hiccup mode OFF time	All converters disabled. After t_{OFF_HICCUP} elapses, all converters go through sequencing again.		11		ms
VOV_BUCKX	Threshold voltage for buck over voltage	Output rising (high-side FET is forced off)		106%
VOV_BUCKX	Threshold voltage for buck over voltage	Output falling (high-side FET is allowed to switch)		104%
t_RP	Minimum reset period	TPS65251-1		1000		ms
		TPS65251-2		32
		TPS65251-3		256
THERMAL SHUTDOWN
T_TRIP	Thermal shutdown trip point	Rising temperature		160		°C
T_HYST	Thermal shutdown hysteresis	Device restarts		20		°C
t_{TRIP_DEGLITCH}	Thermal shutdown deglitch		100		120	µs