SLVSAA4G
June 2010 – February 2018
TPS65251
PRODUCTION DATA.
1
Features
2
Applications
3
Description
Device Images
Typical Application Schematic
4
Revision History
5
Description (continued)
6
Pin Configuration and Functions
Pin Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Adjustable Switching Frequency
8.3.2
Synchronization
8.3.3
Out-of-Phase Operation
8.3.4
Delayed Start-Up
8.3.5
Soft-Start Time
8.3.6
Adjusting the Output Voltage
8.3.7
Input Capacitor
8.3.8
Bootstrap Capacitor
8.3.9
Error Amplifier
8.3.10
Loop Compensation
8.3.11
Slope Compensation
8.3.12
Powergood
8.3.13
Current Limit Protection
8.3.14
Overvoltage Transient Protection
8.3.15
Thermal Shutdown
8.4
Device Functional Modes
8.4.1
Low-Power Mode Operation
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Loop Compensation Circuit
9.2.2.2
Selecting the Switching Frequency
9.2.2.3
Output Inductor Selection
9.2.2.4
Output Capacitor
9.2.2.5
Input Capacitor
9.2.2.6
Soft-Start Capacitor
9.2.2.7
Bootstrap Capacitor Selection
9.2.2.8
Adjustable Current Limiting Resistor Selection
9.2.2.9
Output Voltage and Feedback Resistors Selection
9.2.2.10
Compensation
9.2.2.11
3.3-V and 6.5-V LDO Regulators
9.2.3
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
11.3
Power Dissipation
12
Device and Documentation Support
12.1
Receiving Notification of Documentation Updates
12.2
Community Resources
12.3
Trademarks
12.4
Electrostatic Discharge Caution
12.5
Glossary
13
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RHA|40
MPQF135D
Thermal pad, mechanical data (Package|Pins)
RHA|40
QFND227K
Orderable Information
slvsaa4g_oa
slvsaa4g_pm
9.2.2
Detailed Design Procedure