SLVSCN5B june   2014  – may 2023 TPS65262-1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Adjusting the Output Voltage
      2. 8.3.2  Enable and Adjusting UVLO
      3. 8.3.3  Soft-Start Time
      4. 8.3.4  Power-Up Sequencing
        1. 8.3.4.1 External Power Sequencing
        2. 8.3.4.2 Automatic Power Sequencing
      5. 8.3.5  V7V Low Dropout Regulator and Bootstrap
      6. 8.3.6  Out-of-Phase Operation
      7. 8.3.7  Output Overvoltage Protection (OVP)
      8. 8.3.8  PSM
      9. 8.3.9  Slope Compensation
      10. 8.3.10 Overcurrent Protection (OCP)
        1. 8.3.10.1 High-Side MOSFET OCP
        2. 8.3.10.2 Low-Side MOSFET OCP
      11. 8.3.11 Power Good
      12. 8.3.12 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation With VIN < 4.5 V (Minimum VIN)
      2. 8.4.2 Operation With EN Control
      3. 8.4.3 Operation at Light Loads
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Inductor Selection
        2. 9.2.2.2 Output Capacitor Selection
        3. 9.2.2.3 Input Capacitor Selection
        4. 9.2.2.4 Loop Compensation
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

GUID-FAA253A0-9482-473D-BE10-38822A44543A-low.gif
(There is no electric signal down bonded to thermal pad inside IC. Exposed thermal pad must be soldered to PCB for optimal thermal performance.)
Figure 6-1 RHB Package32 Pins(Top View)
Table 6-1 Pin Functions
PIN DESCRIPTION
NAME NO.
LVIN2 1 Input power supply for LDO2. Connect LVIN2 pin as close as possible to the (+) terminal of an input ceramic capacitor (suggest 1 µF).
LOUT2 2 LDO2 output. Connect LOUT2 pin as close as possible to the (+) terminal of an output ceramic capacitor (suggest
1 µF).
LFB2 3 Feedback Kelvin sensing pin for LDO2 output voltage. Connect this pin to LDO2 resistor divider.
LEN2 4 Enable for LDO2. Float to enable.
PGOOD 5 An open-drain output, asserts low if the output voltage of any buck is beyond regulation range due to thermal shutdown, overcurrent, undervoltage, or ENx shut down.
MODE 6 When high, an automatic power-up or power-down sequence is provided according to the states of EN1, EN2, and EN3 pins.
FB2 7 Feedback Kelvin sensing pin for buck2 output voltage. Connect this pin to buck2 resistor divider.
EN2 8 Enable for buck2. Float to enable. Can use this pin to adjust the input undervoltage lockout of buck2 with a resistor divider.
BST2 9 Boot-strapped supply to the high-side floating gate driver in buck2. Connect a capacitor (recommend 47 nF) from BST2 pin to LX2 pin.
LX2 10 Switching node connection to the inductor and bootstrap capacitor for buck2. The voltage swing at this pin is from a diode voltage below the ground up to VIN2 voltage.
PGND2 11 Power ground connection of buck2. Connect PGND2 pin as close as possible to the (–) terminal of VIN2 input ceramic capacitor.
VIN2 12 Input power supply for buck2. Connect VIN2 pin as close as possible to the (+) terminal of an input ceramic capacitor (suggest 10 µF).
VIN3 13 Input power supply for buck3. Connect VIN3 pin as close as possible to the (+) terminal of an input ceramic capacitor (suggest 10 µF).
PGND3 14 Power ground connection of buck3. Connect PGND3 pin as close as possible to the (–) terminal of VIN3 input ceramic capacitor.
LX3 15 Switching node connection to the inductor and bootstrap capacitor for buck3. The voltage swing at this pin is from a diode voltage below the ground up to VIN3 voltage.
BST3 16 Boot-strapped supply to the high-side floating gate driver in buck3. Connect a capacitor (recommend 47 nF) from BST3 pin to LX3 pin.
EN3 17 Enable for buck3. Float to enable. Can use this pin to adjust the input undervoltage lockout of buck3 with a resistor divider.
FB3 18 Feedback Kelvin sensing pin for buck3 output voltage. Connect this pin to buck3 resistor divider.
AGND 19 Analog ground common to buck controllers and other analog circuits. It must be routed separately from high-current power grounds to the (–) terminal of the bypass capacitor of input voltage VIN.
V7V 20 Internal LDO for gate driver and internal controller. Connect a 10-µF capacitor from the pin to power ground.
COMP1 21 Error amplifier output and loop compensation pin for buck1. Connect a series resistor and capacitor to compensate the control loop of buck1 with peak current PWM mode.
SS1 22 Soft-start and tracking input for buck1. An internal 5-µA pullup current source is connected to this pin. The soft-start time can be programmed by connecting a capacitor between this pin and ground.
FB1 23 Feedback Kelvin sensing pin for buck1 output voltage. Connect this pin to buck1 resistor divider.
EN1 24 Enable for buck1. Float to enable. Can use this pin to adjust the input undervoltage lockout of buck1 with a resistor divider.
BST1 25 Boot-strapped supply to the high side floating gate driver in buck1. Connect a capacitor (recommend 47 nF) from BST1 pin to LX1 pin.
LX1 26 Switching node connection to the inductor and bootstrap capacitor for buck1. The voltage swing at this pin is from a diode voltage below the ground up to VIN1 voltage.
PGND1 27 Power ground connection of Buck1. Connect PGND1 pin as close as possible to the (–) terminal of VIN1 input ceramic capacitor.
VIN1 28 Input power supply for buck1. Connect VIN1 pin as close as possible to the (+) terminal of an input ceramic capacitor (suggest 10 µF).
LEN1 29 Enable for LDO1. Float to enable.
LFB1 30 Feedback Kelvin sensing pin for LDO1 output voltage. Connect this pin to LDO1 resistor divider.
LOUT1 31 LDO1 output. Connect LOUT1 pin as close as possible to the (+) terminal of an output ceramic capacitor (suggest
1 µF).
LVIN1 32 Input power supply for LDO1. Connect LVIN1 pin as close as possible to the (+) terminal of an input ceramic capacitor (suggest 1 µF).
PAD — There is no electric signal down bonded to thermal pad inside IC. Exposed thermal pad must be soldered to PCB for optimal thermal performance.