SLVSCF9D january   2014  – may 2023 TPS65262

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Adjusting the Output Voltage
      2. 7.3.2  Enable and Adjusting Undervoltage Lockout
      3. 7.3.3  Soft-Start Time
      4. 7.3.4  Power-Up Sequencing
        1. 7.3.4.1 External Power Sequencing
        2. 7.3.4.2 Automatic Power Sequencing
      5. 7.3.5  V7V Low Dropout Regulator and Bootstrap
      6. 7.3.6  Out-of-Phase Operation
      7. 7.3.7  Output Overvoltage Protection (OVP)
      8. 7.3.8  PSM
      9. 7.3.9  Slope Compensation
      10. 7.3.10 Overcurrent Protection
        1. 7.3.10.1 High-Side MOSFET Overcurrent Protection
        2. 7.3.10.2 Low-Side MOSFET Overcurrent Protection
      11. 7.3.11 Power Good
      12. 7.3.12 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation With VIN < 4.5 V (Minimum VIN)
      2. 7.4.2 Operation With EN Control
      3. 7.4.3 Operation at Light Loads
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Inductor Selection
        2. 8.2.2.2 Output Capacitor Selection
        3. 8.2.2.3 Input Capacitor Selection
        4. 8.2.2.4 Loop Compensation
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.1 Overview

The TPS65262 is a monolithic triple synchronous step-down (buck) converter with 3-A/1-A/1-A output currents. A wide 4.5- to 18-V input supply voltage range encompasses most intermediate bus voltages operating off 5-, 9-, 12-, or 15-V power bus. The feedback voltage reference for each buck is 0.6V. Each buck is independent with dedicated enable, soft-start and loop compensation.

The TPS65262 implements a constant frequency, peak current mode control that simplifies external loop compensation. The switching frequency is fixed 600 kHz. The switching clock of buck1 is 180° out-of-phase operation from the clocks of buck2 and buck3 channels to reduce input current ripple, input capacitor size and power supply induced noise.

The TPS65262 has been designed for safe monotonic startup into pre-biased loads. The default start up is when VIN is typically 4.5 V. The ENx pin also can be used to adjust the input voltage undervoltage lockout (UVLO) with an external resistor divider. In addition, the ENx pin has an internal 3.6-µA current source, so the EN pin can be floating for automatically powering up the converters.

The TPS65262 reduces the external component count by integrating the bootstrap circuit. The bias voltage for the integrated high-side MOSFET is supplied by a capacitor between the BST and LX pins. A UVLO circuit monitors the bootstrap capacitor voltage VBST-VLX in each buck. When VBST-VLX voltage drops to the threshold, LX pin is pulled low to recharge the bootstrap capacitor. The TPS65262 can operate at 100% duty cycle as long as the bootstrap capacitor voltage is higher than the BOOT-LX UVLO threshold which is typically 2.1 V.

The TPS65262 features a PGOOD pin to supervise each output voltage of buck converters. The TPS65262 has power good comparators with hysteresis, which monitor the output voltages through feedback voltages. When all bucks are in regulation range and power sequence is done, PGOOD is asserted to high.

The SS (soft start/tracking) pin is used to minimize inrush currents during power up. A small value capacitor or resistor divider is coupled to the pin for soft start or voltage tracking.

At light loading, TPS65262 automatically operates in pulse skipping mode (PSM) to save power.

The TPS65262 integrates low drop-out voltage linear regulators (LDO) with input voltage from 1.3 to 18 V, independent enable and adjustable outputs, up to 200 mA for LDO1 and 100 mA for LDO2 continuous output current.

The TPS65262 is protected from overload and over temperature fault conditions. The converter minimizes excessive output overvoltage transients by taking advantage of the power good comparator. When the output is over, the high-side MOSFET is turned off until the internal feedback voltage is lower than 105% of the 0.6-V reference voltage. The TPS65262 implements both high-side MOSFET overload protection and bidirectional low-side MOSFET overload protections to avoid inductor current runaway. If the over current condition has lasted for more than the OC wait time (0.5 ms), the converter will shut down and restart after the hiccup time (14 ms). The TPS65262 shuts down if the junction temperature is higher than thermal shutdown trip point 160°C. When the junction temperature drops 20°C (typical) below the thermal shutdown trip point, the TPS65262 will be restarted under control of the soft-start circuit automatically.

The TPS65262 is available in a 32-lead thermally-enhanced VQFN (RHB) package.