SLVSDY9A March   2017  – November 2022 TPS65263-1Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Adjusting the Output Voltage
      2. 7.3.2  Enable and Adjusting UVLO
      3. 7.3.3  Soft-Start Time
      4. 7.3.4  Power-Up Sequencing
      5. 7.3.5  V7V Low-Dropout Regulator and Bootstrap
      6. 7.3.6  Out-of-Phase Operation
      7. 7.3.7  Output Overvoltage Protection (OVP)
      8. 7.3.8  PSM
      9. 7.3.9  Slope Compensation
      10. 7.3.10 Overcurrent Protection
        1. 7.3.10.1 High-Side MOSFET Overcurrent Protection
        2. 7.3.10.2 Low-Side MOSFET Overcurrent Protection
      11. 7.3.11 Power Good
        1. 7.3.11.1 Adjustable Switching Frequency
      12. 7.3.12 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Serial Interface Description
      2. 7.4.2 I2C Update Sequence
    5. 7.5 Register Maps
      1. 7.5.1 VOUT2_SEL: Vout2 Voltage Selection Register (Address = 0x01H)
      2. 7.5.2 VOUT1_COM: Buck1 Command Register (offset = 0x03H)
      3. 7.5.3 VOUT2_COM: Buck2 Command Register (offset = 0x04H)
      4. 7.5.4 VOUT3_COM: Buck3 Command Register (offset = 0x05H)
      5. 7.5.5 SYS_STATUS: System Status Register (offset = 0x06H)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Inductor Selection
        2. 8.2.2.2 Output Capacitor Selection
        3. 8.2.2.3 Input Capacitor Selection
        4. 8.2.2.4 Loop Compensation
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The TPS65263-1Q1 incorporates triple-synchronous buck converters with 4.0- to 18-V wide input voltage. The converter with constant frequency peak current mode is designed to simplify its application while giving designers options to optimize the system according to targeted applications. The switching frequency of the converters is adjustable from 200 kHz to 2.3 MHz with an external resistor. 180° out-of-phase operation between buck1 and buck2, buck3 (buck2 and buck3 run in phase) minimizes the input filter requirements.

The initial start-up voltage of each buck can be set with external feedback resistors. The output voltage of buck2 can be dynamically scaled from 0.68 to 1.95 V in 10-mV steps with I2C-controlled 7 bits VID. The VID voltage transition slew rate is programmable with 3-bits control through I2C bus to optimize overshoot, undershoot during VID voltage transition.

Each buck in TPS65263-1Q1 can be I2C controlled for enabling and disabling output voltage, setting the pulse skipping mode (PSM) or forced continuous current (FCC) mode at light load condition and reading the power-good status, overcurrent warning, and die temperature warning.

The TPS65263-1Q1 features overvoltage, overcurrent, short-circuit, and overtemperature protection.

Package Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
TPS65263-1Q1 RHB (VQFN, 32) 5.00 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
GUID-897E7919-14E8-4813-ABBA-307718BDB271-low.gifApplication Schematic
GUID-C78D066D-8951-401A-8E0C-34682495F024-low.gifEfficiency vs Output Load