SLVSD86B december   2015  – may 2023 TPS65265

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Adjusting the Output Voltage
      2. 8.3.2  Mix PGOOD, PG_DLY Functions
        1. 8.3.2.1 Programmable PGOOD DELAY
        2. 8.3.2.2 Relay Control
      3. 8.3.3  Enable and Adjusting UVLO
      4. 8.3.4  Soft-Start Time
      5. 8.3.5  Power-Up Sequencing
        1. 8.3.5.1 External Power Sequencing
        2. 8.3.5.2 Automatic Power Sequencing
      6. 8.3.6  V7V Low Dropout Regulator and Bootstrap
      7. 8.3.7  Out of Phase Operation
      8. 8.3.8  Output Overvoltage Protection (OVP)
      9. 8.3.9  PSM
      10. 8.3.10 Slope Compensation
      11. 8.3.11 Overcurrent Protection
        1. 8.3.11.1 High-Side MOSFET Overcurrent Protection
        2. 8.3.11.2 Low-Side MOSFET Overcurrent Protection
      12. 8.3.12 Adjustable Switching Frequency
      13. 8.3.13 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation With VIN < 4 V (Minimum VIN)
      2. 8.4.2 Operation With EN Control
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Inductor Selection
        2. 9.2.2.2 Output Capacitor Selection
        3. 9.2.2.3 Input Capacitor Selection
        4. 9.2.2.4 Loop Compensation
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The TPS65265 incorporates triple synchronous buck converters with 4.5-V to 17-V wide input voltage range that encompassed most intermediate bus voltage operating off 5-, 9-, 12- or 15-V power bus or battery. The converter with constant frequency peak current mode is designed to simplify its application while giving designers options to optimize the system according to targeted applications. The switching frequency of the converters can be adjustable from 250 kHz to 2.3 MHz with an external resistor or external clock. 120° out-of-phase operation between Buck1, Buck2, and Buck3 minimizes the input filter requirements.

The TPS65265 operates in pulse skipping mode (PSM) with driving MODE pin to high or leaving float and operates in force continuous current mode (FCC) with connecting MODE pin to GND. PSM mode provides high efficiency by reducing switching losses at light load and FCC mode reduces noise susceptibility and RF interference.

The TPS65265 is available in a 32-pin thermal enhanced QFN (RHB) 5-mm × 5-mm thin package.

Package Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
TPS65265 RHB (VQFN, 32) 5.00 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
GUID-D5E399D1-2663-4528-8302-0971E9C42FD1-low.svgSimplified Application Circuit
GUID-6E6AD051-6B19-4190-8509-389242C26F71-low.gifEfficiency vs Output Load