TPS65266-1 2.7 to 6-V Input Voltage, 3-A/2-A/2-A Output Current Triple Synchronous Step-Down Converter

SPACE

Simplified Application Schematic

Efficiency vs Output Load

7.3.1 Adjusting the Output Voltage

The output voltage of each buck is set with a resistor divider from the output of buck to the FB pin. TI recommends to use 1% tolerance or better resistors.

Figure 21. Voltage Divider Circuit

Equation 1.

To improve efficiency at light loads, consider using larger-value resistors. If the values are too high, the regulator is more sensitive to noise. Table 1 shows the recommended resistor values.

7.3.2 Enable and Adjusting UVLO

The EN1/2/3 pin provides electrical on and off control of the device. After the EN1/2/3 pin voltage exceeds the threshold voltage, the device starts operation. If each ENx pin voltage is pulled below the threshold voltage, the regulator stops switching and enters low I_q state.

The EN pin has an internal pullup current source, allowing the user to float the EN pin for enabling the device. If an application requires controlling the EN pin, use open-drain or open-collector output logic to interface with the pin.

The device implements internal UVLO circuitry on the VINQ pin. The device is disabled when the VINQ pin voltage falls below the internal VIN UVLO threshold. The internal VIN UVLO threshold has a hysteresis of 200 mV. If an application requires either a higher UVLO threshold on the VINQ pin or a secondary UVLO on the VINx, in split-rail applications, then the ENx pin can be configured as shown in Figure 22, Figure 23, and Figure 24. When using the external UVLO function, TI recommends to set the hysteresis to be >200 mV.

The EN pin has a small pullup current I_p, which sets the default state of the pin to enable when no external components are connected. The pullup current is also used to control the voltage hysteresis for the UVLO function because it increases by I_h after the EN pin crosses the enable threshold. Calculate the UVLO thresholds using Equation 2 and Equation 3.

Equation 2.

Equation 3.

where

• I_h = 3.2 µA
• I_p = 2.1 µA
• V_ENRISING = 1.2 V
• V_ENFALLING = 1.15 V

Figure 22. Adjustable VINQ UVLO

Figure 23. Adjustable VIN UVLO, VINQ > 2.7 V

Figure 24. Adjustable VIN and VINQ UVLO

7.3.3 Soft-Start Time

The voltage on the respective SS pin controls the start-up of buck output. When the voltage on the SS pin is less than the internal 0.6-V reference, the TPS65266-1 regulates the internal feedback voltage to the voltage on the SS pin instead of 0.6 V. The SS pin can be used to program an external soft-start function or to allow output of buck to track another supply during start-up. The device has an internal pullup current source of 5.5 μA (typical) that charges an external soft-start capacitor to provide a linear ramping voltage at SS pin. The TPS65266-1 regulates the internal feedback voltage to the voltage on the SS pin, allowing VOUT to rise smoothly from 0 V to its regulated voltage without inrush current. Calculate the approximate soft-start time with Equation 4.

Equation 4.

Many of the common power-supply sequencing methods can be implemented using the SSx and ENx pins. Figure 25 shows the method implementing ratiometric sequencing by connecting the SSx pins of three buck channels together. The regulator outputs ramp up and reach regulation at the same time. When calculating the soft-start time, the pullup current source must be tripled in Equation 4.

Figure 25. Ratiometric Power-Up Using SSx Pins

Simultaneous power-supply sequencing can be implemented by connecting capacitor to SSx pin, shown in Figure 26. Using Equation 4 and Equation 5, calculate the capacitors.

Equation 5.

Figure 26. Simultaneous Startup Sequence Using SSx Pins

7.3.4 Power-Up Sequencing

The TPS65266-1 has a dedicated enable pin and soft-start pin for each converter. The converter enable pins are biased by a current source that allows for easy sequencing by the addition of an external capacitor. Enable pins have a discharge function, which ensures power-up sequencing is effective at quickly powering down and up status. Disabling the converter with an active pulldown transistor on the ENs pin allows for a predictable power-down timing operation. Figure 27 shows the timing diagram of a typical buck power-up sequence with connecting a capacitor at ENx pin.

When VINQ pin voltage rises to about 1 V, the internal EN turns on and a typical 1.4-µA current is charging ENx pin from input supply. If any of the EN pin voltages reaches 0.5 V when powered up, three EN pin discharge functions are triggered and keep 2 ms with discharge resistor around 1.2 kΩ to GND, then a 2.1-µA pullup current is sourcing ENx. After ENx pin voltage reaches to ENx enabling threshold, 3.2-µA hysteresis current sources to the pin to improve noise sensitivity.

Figure 27. Startup Power Sequence

7.3.5 Bootstrap Voltage and BST-LX UVLO

Each high-side MOSFET driver is biased from the floating bootstrap capacitor, CB, shown in Figure 28, which is normally recharged during each cycle through an internal low-side MOSFET or the body diode of a low-side MOSFET when the high-side MOSFET turns off. The boot capacitor is charged when the BST pin voltage is less than VIN and BST-LX voltage is below regulation. The recommended value of this ceramic capacitor is 47 nF. TI recommends a ceramic capacitor with an X7R- or X5R-grade dielectric with a voltage rating of 10 V or higher because of the stable characteristics over temperature and voltage.

To improve dropout, the device is designed to operate at 100% duty cycle as long as the BST to LX pin voltage is greater than the BST-LX UVLO threshold, which is typically 2.1 V. When the voltage between BST and LX drops below the BST-LX UVLO threshold, the high-side MOSFET is turned off and the low-side MOSFET is turned on allowing the boot capacitor to be recharged.

Figure 28. Bootstrap Voltage and Diagram

7.3.6 Out of Phase Operation

To reduce input ripple current, the switch clock of buck1 is 180° out-of-phase from the clock of buck2 and buck3. This enables the system by having less input current ripple to reduce input capacitors’ size, cost, and EMI.

7.3.7 Output Overvoltage Protection (OVP)

The device incorporates an OVP circuit to minimize output voltage overshoot. When the output is overloaded, the error amplifier compares the actual output voltage to the internal reference voltage. If the FB pin voltage is lower than the internal reference voltage for a considerable time, the output of the error amplifier demands maximum output current. After the condition is removed, the regulator output rises and the error amplifier output transitions to the steady-state voltage. In some applications with small output capacitance, the load can respond faster than the error amplifier. This leads to the possibility of an output overshoot. Each buck compares the FB pin voltage to the OVP threshold. If the FB pin voltage is greater than the OVP threshold, the high-side MOSFET is turned off preventing current from flowing to the output and minimizing output overshoot. When the FB voltage drops lower than the OVP threshold, the high-side MOSFET turns on at the next clock cycle.

7.3.8 Slope Compensation

To prevent the subharmonic oscillations when the device operates at duty cycles greater than 50%, the TPS65266-1 adds built-in slope compensation, which is a compensating ramp to the switch current signal.

7.3.9 Overcurrent Protection

The device is protected from overcurrent conditions by cycle-by-cycle current limiting on both the high-side MOSFET and low-side MOSFET.

7.3.9.2 Low-Side MOSFET Overcurrent Protection

While the low-side MOSFET is turned on, its conduction current is monitored by the internal circuitry. During normal operation the low-side MOSFET sources current to the load. At the end of every clock cycle, the low-side MOSFET sourcing current is compared to the internally set low-side sourcing current limit. If the low-side sourcing current is exceeded, the high-side MOSFET is not turned on and the low-side MOSFET stays on for the next cycle. The high-side MOSFET is turned on again when the low-side current is below the low-side sourcing current limit at the start of a cycle.

The low-side MOSFET may also sink current from the load. If the low-side sinking current limit is exceeded, the low-side MOSFET is turned off immediately for the rest of that clock cycle. In this scenario, both MOSFETs are off until the start of the next cycle.

Furthermore, if an output overload condition (as measured by the COMP pin voltage) has lasted for more than the hiccup wait time, which is programmed for 512 cycles (typical) shown in Figure 29, the device shuts down itself and restarts after the hiccup time of 16382 cycles (typical). The hiccup mode helps to reduce the device power dissipation under a severe overcurrent condition.

Figure 29. Overcurrent Protection

7.3.10 Power Good

The PGOOD pin is an open-drain output. After the feedback voltage of each buck is higher than 95% (rising) of the internal voltage reference, the PGOOD pin pulldown is deasserted and the pin floats. TI recommends to use a pullup resistor between the values of 10 kΩ and 100 kΩ to a voltage source that is 5.0 V or less.

The PGOOD pin is pulled low when any feedback voltage of a buck is lower than 92.5% (falling) of the nominal internal reference voltage. Also, the PGOOD is pulled low if the input voltage is undervoltage locked up, thermal shutdown is asserted, the EN pin is pulled low, or the converter is in a soft-start period.

7.3.11 Adjustable Switching Frequency

The ROSC pin can be used to set the switching frequency by connecting a resistor to GND. The switching frequency of the device is adjustable from 250 kHz to 2.4 MHz.

To determine the ROSC resistance for a given switching frequency, use Equation 6 or the curve in Figure 30. To reduce the solution size, the user should set the switching frequency as high as possible, but consider the tradeoffs of the supply efficiency and minimum controllable on-time.

Equation 6.

Figure 30. ROSC vs Switching Frequency

When an external clock applies to the ROSC pin, the internal phase locked loop (PLL) has been implemented to allow internal clock synchronizing to an external clock between 250 kHz and 2.4 MHz. To implement the clock synchronization feature, connect a square wave clock signal to the ROSC pin with a duty cycle between 20% to 80%. The clock signal amplitude must transition lower than 0.4 V and higher than 2.0 V. The start of the switching cycle is synchronized to the falling edge of the ROSC pin.

In applications where both resistor mode and synchronization mode are needed, the device can be configured as shown in Figure 31. Before an external clock is present, the device works in resistor mode and ROSC resistor sets the switching frequency. When an external clock is present, the synchronization mode overrides the resistor mode. The first time the ROSC pin is pulled above the ROSC high threshold (2.0 V), the device switches from the resistor mode to the synchronization mode and the ROSC pin becomes high impedance as the PLL starts to lock onto the frequency of the external clock. TI does not recommended to switch from synchronization mode back to resistor mode because the internal switching frequency drops to 100 kHz first before returning to the switching frequency set by ROSC resistor.

Figure 31. Works With Resistor Mode and Synchronization Mode

7.3.12 PSM

The TPS65266-1 can enter high-efficiency PSM operation at light load current.

When a controller is enabled for PSM operation, the peak inductor current is sensed and compared with 250-mA current typically. Because the integrated current comparator catches the peak inductor current only, the average load current entering PSM varies with the applications and external output filters. In PSM, the sensed peak inductor current is clamped at 250 mA (see Figure 32).

When a controller operates in PSM, the inductor current is not allowed to reverse. The reverse current comparator turns off the low-side MOSFET when the inductor current reaches 0, preventing it from reversing and going negative.

Due to the delay in the circuit and current comparator tdly (typical 50 nS at V_IN = 5 V), the real peak inductor current threshold to turn off high-side power MOSFET could shift higher depending on inductor inductance and input/output voltages. Calculate the threshold of peak inductor current to turn off high-side power MOSFET with Equation 7.

Equation 7.

When the charge accumulated on V_OUT capacitor is more than loading need, COMP pin voltage drops to low voltage driven by error amplifier. There is an internal comparator at COMP pin. If comp voltage is < 0.35 V, the power stage stops switching to save power.

Figure 32. PSM Current Comparator

7.3.13 Thermal Shutdown

The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds 160°C typically. The device reinitiates the power-up sequence when the junction temperature drops below 140°C typically.

7.4.1 Operation With V_IN < 2.6 V (Minimum V_IN)

The device operates with input voltages above 2.6 V. The maximum UVLO voltage is 2.6 V and will operate at input voltages above 2.6 V. The typical UVLO voltage is 2.45 V and the device may operate at input voltages above that point. The device also may operate at lower input voltages, the minimum UVLO voltage is 2.35 V (rising) and 2.15V (falling). At input voltages below the UVLO minimum voltage, the devices will not operate.

7.4.2 Operation With EN Control

The enable rising edge threshold voltage is 1.2 V typical and 1.26 V maximum. With EN held below that voltage the device is disabled and switching is inhibited. The IC quiescent current is reduced in this state. When input voltage is above the UVLO threshold and the EN voltage is increased above the rising edge threshold, the device becomes active. Switching is enabled, and the soft start sequence is initiated. The device will start at the soft start time determined by the external soft start capacitor as shown in Figure 35 to Figure 37.

8.2.1 Design Requirements

This example details the design of a triple-synchronous step-down converter. The designer must know a few parameters to start the design process. These parameters are typically determined at the system level. For this example, start with the following known parameters in Table 2.

8.2.2 Detailed Design Procedure

8.2.2.1 Output Inductor Selection

To calculate the value of the output inductor, use Equation 8. LIR is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. The inductor ripple current is filtered by the output capacitor. Therefore, choosing high inductor ripple currents impact the selection of the output capacitor because the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion of the designer; however, LIR is normally from 0.1 to 0.3 for the majority of applications.

Equation 8.

For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded. The RMS and peak inductor current can be found from Equation 10 and Equation 11.

Equation 9.

Equation 10.

Equation 11.

The current flowing through the inductor is the inductor ripple current plus the output current. During power-up, faults, or transient load conditions, the inductor current can increase above the calculated peak inductor current level calculated previously. In transient conditions, the inductor current can increase up to the switch current limit of the device. For this reason, the most conservative approach is to specify an inductor with a saturation current rating equal to or greater than the switch current limit rather than the peak inductor current.

8.2.2.2 Output Capacitor Selection

The three primary considerations for selecting the value of the output capacitor are: the output capacitor determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in load current. The output capacitance must be selected based on the most stringent of these three criteria.

The first criterion is the desired response to a large change in the load current. The output capacitor needs to supply the load with current when the regulator cannot. This situation would occur if there are desired hold-up times for the regulator where the output capacitor must hold the output voltage above a certain level for a specified amount of time after the input power is removed. The regulator is also temporarily not able to supply sufficient output current if there is a large, fast increase in the current needs of the load such as a transition from no load to full load. The regulator usually needs two or more clock cycles for the control loop to see the change in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor must be sized to supply the extra current to the load until the control loop responds to the load change. The output capacitance must be large enough to supply the difference in current for two clock cycles while only allowing a tolerable amount of droop in the output voltage. Equation 12 shows the minimum output capacitance necessary to accomplish this.

Equation 12.

where

• ΔIout is the change in output current.
• ƒ_SW is the regulator's switching frequency.
• ΔVout is the allowable change in the output voltage.

Equation 13 calculates the minimum output capacitance needed to meet the output voltage ripple specification.

Equation 13.

where

• ƒ_SW is the switching frequency.
• V_ripple is the maximum allowable output voltage ripple.
• I_ripple is the inductor ripple current.

Equation 14 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple specification.

Equation 14.

Additional capacitance deratings for aging, temperature, and DC bias should be factored in, which increase this minimum value. Capacitors generally have limits to the amount of ripple current they can handle without failing or producing excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor data sheets specify the root mean square (RMS) value of the maximum ripple current. Equation 15 can be used to calculate the RMS ripple current the output capacitor needs to support.

Equation 15.

8.2.2.3 Input Capacitor Selection

The TPS65266-1 requires a high-quality ceramic, type X5R or X7R, input decoupling capacitor of at least 10 μF of effective capacitance on the VIN input voltage pins. In some applications, additional bulk capacitance may also be required for the VIN input. The effective capacitance includes any DC bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current rating greater than the maximum input current ripple of the TPS65266-1. Calculate the input ripple current using Equation 16.

Equation 16.

The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors because they have a high capacitance-to-volume ratio and are fairly stable over temperature. The output capacitor must also be selected with the DC bias taken into account. The capacitance value of a capacitor decreases as the DC bias across a capacitor increases. The input capacitance value determines the input ripple voltage of the regulator. Calculate the input voltage ripple using Equation 17.

Equation 17.

8.2.2.4 Loop Compensation

The TPS65266-1 incorporates a peak current mode control scheme. The error amplifier is a transconductance amplifier with a gain of 290 µS. A typical type II compensation circuit adequately delivers a phase margin between 30° and 90°. C_b adds a high-frequency pole to attenuate high-frequency noise when needed. To calculate the external compensation components, follow these steps.

1. Select switching frequency, ƒ_SW, that is appropriate for application depending on L and C sizes, output ripple, EMI, and so forth. Switching frequency between 500 kHz to 1.5 MHz gives best trade-off between performance and cost. To optimize efficiency, lower switching frequency is desired.
2. Set up crossover frequency, ƒ_c, which is typically between 1 / 5 and 1 / 20 of ƒ_SW.
3. R_C can be determined by:
Equation 18.
where
• G_{m_EA} is the error amplifier gain (290 µS).
• G_{m_PS} is the power stage voltage to current conversion gain (10 A/V).
4. Calculate C_C by placing a compensation zero at or before the dominant pole
Equation 19.
5. Optional C_b can be used to cancel the zero from the ESR associated with C_O.
Equation 20.
6. Type III compensation can be implemented with the addition of one capacitor, C₁. This allows for slightly higher loop bandwidths and higher phase margins. If used, C₁ is calculated from Equation 21.
Equation 21.

Figure 34. DC/DC Loop Compensation

8.2.3 Application Curves

Figure 35. Buck1, Soft-Start, Iout = 3 A

Figure 36. Buck2, Soft-Start, Iout = 2 A

Figure 37. Buck3, Soft-Start, Iout = 2 A

Figure 39. Buck2, Output Voltage Ripple, Iout = 2 A

	SR = 0.25 A/µs

Figure 41. Buck1, Load Transient, 0.75 to 1.5 A

	SR = 0.25 A/µs

Figure 43. Buck2, Load Transient, 0.5 to 1.0 A

	SR = 0.25 A/µs

Figure 45. Buck3, Load Transient, 0.5 to 1.0 A

Figure 47. Buck1, Hiccup and Recovery

Figure 49. Buck3, Hiccup and Recovery

Figure 38. Buck1, Output Voltage Ripple, Iout = 3 A

Figure 40. Buck3, Output Voltage Ripple, Iout = 2 A

	SR = 0.25 A/µs

Figure 42. Buck1, Load Transient, 1.5 to 2.25 A

	SR = 0.25 A/µs

Figure 44. Buck2, Load Transient, 1.0 to 1.5 A

	SR = 0.25 A/µs

Figure 46. Buck3, Load Transient, 1.0 to 1.5 A

Figure 48. Buck2, Hiccup and Recovery

Figure 50. 180° Out of Phase

11.1.1 Related Parts