SLVSE48C january   2018  – may 2023 TPS65268-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Adjusting the Output Voltage
      2. 7.3.2  Enable and Adjusting UVLO
      3. 7.3.3  Soft-Start Time
      4. 7.3.4  Power-Up Sequencing
      5. 7.3.5  V7V Low-Dropout Regulator and Bootstrap
      6. 7.3.6  Out-of-Phase Operation
      7. 7.3.7  Output Overvoltage Protection (OVP)
      8. 7.3.8  Slope Compensation
      9. 7.3.9  Overcurrent Protection
        1. 7.3.9.1 High-Side MOSFET Overcurrent Protection
        2. 7.3.9.2 Low-Side MOSFET Overcurrent Protection
      10. 7.3.10 Power Good
        1. 7.3.10.1 Adjustable Switching Frequency
      11. 7.3.11 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Standby Operation
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Inductor Selection
        2. 8.2.2.2 Output Capacitor Selection
        3. 8.2.2.3 Input Capacitor Selection
        4. 8.2.2.4 Loop Compensation
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2.4 Loop Compensation

The TPS65268-Q1 device incorporates a peak current-mode control scheme. The error amplifier is a transconductance amplifier with a gain of 300 µS. A typical type II compensation circuit adequately delivers a phase margin from 40° to 90°. The Cb capacitor adds a high-frequency pole to attenuate high-frequency noise when needed. To calculate the external compensation components, follow these steps:

  1. Select a switching frequency, fSW, that is appropriate for the application depending on the inductor size, capacitor size, output ripple, EMI, and so forth. Selecting the switching frequency is a trade-off between performance and cost. To achieve a smaller size and lower cost, a higher switching frequency is desired. To optimize efficiency, a lower switching frequency is desired.
  2. Set up the crossover frequency, fC, which is typically from 1/5 to 1/20 of fSW.
  3. Use Equation 16 to calculate the value of RC.
    Equation 16. GUID-B438665A-3FA7-41D1-8A98-6C889E138F14-low.gif

    where

    • Gm_EA is the error amplifier gain (300 µS).
    • Gm_PS is the power stage voltage to current conversion gain (7.4 A/V).
  4. Use Equation 17 to calculate the value Cc by placing a compensation zero at or before the dominant pole ( GUID-F0FA51A7-6350-463D-A927-14D11D083968-low.gif ).
    Equation 17. GUID-C64F7814-21D0-40C3-A1D7-399B904FFBEF-low.gif
  5. Optional: Use Equation 18 to calculate the value of CB capacitor to cancel the zero from the ESR associated with CO.
    Equation 18. GUID-85D7EABD-2BE7-43E0-91B5-63D4F482FE66-low.gif
  6. Optional: Implement type III compensation with the addition of one capacitor, C1. This implementation allows for slightly higher loop bandwidths and higher phase margins. If used, used Equation 19 to calculate the value of C1.
    Equation 19. GUID-0818AB63-16C0-4E35-931D-6B9997381B36-low.gif
GUID-6CAE8273-86DE-432B-BC6A-8AEEC7E5FF71-low.gifFigure 8-2 DC-DC Loop Compensation