SLVSE48C january   2018  – may 2023 TPS65268-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Adjusting the Output Voltage
      2. 7.3.2  Enable and Adjusting UVLO
      3. 7.3.3  Soft-Start Time
      4. 7.3.4  Power-Up Sequencing
      5. 7.3.5  V7V Low-Dropout Regulator and Bootstrap
      6. 7.3.6  Out-of-Phase Operation
      7. 7.3.7  Output Overvoltage Protection (OVP)
      8. 7.3.8  Slope Compensation
      9. 7.3.9  Overcurrent Protection
        1. 7.3.9.1 High-Side MOSFET Overcurrent Protection
        2. 7.3.9.2 Low-Side MOSFET Overcurrent Protection
      10. 7.3.10 Power Good
        1. 7.3.10.1 Adjustable Switching Frequency
      11. 7.3.11 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Standby Operation
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Inductor Selection
        2. 8.2.2.2 Output Capacitor Selection
        3. 8.2.2.3 Input Capacitor Selection
        4. 8.2.2.4 Loop Compensation
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-48215135-5C07-4323-9B45-E424F68066F8-low.svg
No electric signal is down bonded to thermal pad inside the device. Exposed thermal pad must be soldered to PCB for optimal thermal performance.
Figure 5-1 RHB Package32-Pin VQFN With Exposed Thermal PadTop View
Table 5-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NO. NAME
1 EN3 I Enable for BUCK3. Float to enable. Use this pin to adjust the UVLO input voltage of BUCK3 with a resistor divider.
2 AGND G Analog ground common to buck controllers and other analog circuits. This pin must be routed separately from high-current power grounds to the negative pin of bypass capacitor of input voltage (VIN).
3
4
5
6 FB2 I Feedback Kelvin sensing pin for BUCK2 output voltage. Connect this pin to the BUCK2 resistor divider.
7 COMP2 O Error amplifier output and loop compensation pin for BUCK2. Connect a series resistor and capacitor to compensate the control loop of BUCK2 with peak-current PWM mode.
8 SS2 O Soft-start and tracking input for BUCK2. An internal 5.2-µA pullup current source is connected to this pin. The soft-start time can be programmed by connecting a capacitor between this pin and ground.
9 BST2 O Boot-strapped supply to the high-side floating gate driver in BUCK2. Connect a capacitor (recommended value of 47 nF) from the BST2 pin to LX2 pin.
10 LX2 O Switching node connection to the inductor and bootstrap capacitor for BUCK2. The voltage swing at this pin is from a diode voltage below the ground up to the PVIN2 voltage.
11 PGND2 G Power ground connection of BUCK2. Connect the PGND2 pin as close as possible to the negative pin of VIN2 input ceramic capacitor.
12 PVIN2 P Input power supply for BUCK2. Connect the PVIN2 pin as close as possible to the positive pin of an input ceramic capacitor (recommended value of 10 µF).
13 PVIN3 P Input power supply for BUCK3. Connect the PVIN3 pin as close as possible to the positive pin of an input ceramic capacitor (recommended value of 10 µF).
14 PGND3 G Power ground connection of BUCK3. Connect the PGND3 pin as close as possible to the negative pin of the VIN3 input ceramic capacitor.
15 LX3 O Switching node connection to the inductor and bootstrap capacitor for BUCK3. The voltage swing at this pin is from a diode voltage below the ground up to the PVIN3 voltage.
16 BST3 O Boot-strapped supply to the high-side floating gate driver in BUCK3. Connect a capacitor (recommended value of 47 nF) from the BST3 pin to LX3 pin.
17 SS3 O Soft-start and tracking input for BUCK3. An internal 5.2-µA pullup current source is connected to this pin. The soft-start time can be programmed by connecting a capacitor between this pin and ground.
18 COMP3 O Error amplifier output and loop compensation pin for BUCK3. Connect a series resistor and capacitor to compensate the control loop of BUCK3 with peak-current PWM mode.
19 FB3 I Feedback Kelvin sensing pin for BUCK3 output voltage. Connect this pin to the BUCK3 resistor divider.
20 PGOOD O Output voltage supervision pin. When all buck converters are in the regulation range of the PGOOD monitor, the PGOOD pin is asserted high.
21 ROSC O Clock frequency adjustment pin. Connect a resistor from this pin to ground to adjust the clock frequency. When connected to an external clock, the internal oscillator synchronizes to the external clock.
22 FB1 I Feedback Kelvin sensing pin for BUCK1 output voltage. Connect this pin to the BUCK1 resistor divider.
23 COMP1 O Error amplifier output and loop compensation pin for BUCK1. Connect a series resistor and capacitor to compensate the control loop of BUCK1 with peak current PWM mode.
24 SS1 O Soft-start and tracking input for BUCK1. An internal 5.2-µA pullup current source is connected to this pin. The soft-start time can be programmed by connecting a capacitor between this pin and ground.
25 BST1 O Boot-strapped supply to the high-side floating gate driver in BUCK1. Connect a capacitor (recommended value of 47 nF) from the BST1 pin to LX1 pin.
26 LX1 O Switching node connection to the inductor and bootstrap capacitor for BUCK1. The voltage swing at this pin is from a diode voltage below the ground up to the PVIN1 voltage.
27 PGND1 G Power ground connection of BUCK1. Connect the PGND1 pin as close as possible to the negative pin of PVIN1 input ceramic capacitor.
28 PVIN1 P Input power supply for BUCK1. Connect the PVIN1 pin as close as possible to the positive pin of an input ceramic capacitor (suggest 10 µF).
29 VIN P Buck controller power supply
30 V7V O Internal LDO regulator for gate driver and internal controller. Connect a 10-µF capacitor from the pin to power ground.
31 EN1 I Enable for BUCK1. Float to enable. Use this pin to adjust the UVLO input voltage of BUCK1 with a resistor divider.
32 EN2 I Enable for BUCK2. Float to enable. Use this pin to adjust the UVLO input voltage of BUCK2 with a resistor divider.
— PAD — No electric signal is down bonded to thermal pad inside the device. Exposed thermal pad must be soldered to PCB for optimal thermal performance.
(1) I = Input, O = Output, P = Supply, G = Ground